diff options
| author | Ben Shelton <benjamin.h.shelton@intel.com> | 2020-11-20 16:39:33 -0800 |
|---|---|---|
| committer | Tony Nguyen <anthony.l.nguyen@intel.com> | 2021-02-08 16:27:01 -0800 |
| commit | 4f8a14976aa4b3304e83ff9b4e0a466a3131df3c (patch) | |
| tree | 2cedd9bfe03e46459e0aa8b5ff1396a8471e6548 /drivers/net/ethernet/intel/ice/ice_type.h | |
| parent | b126bd6bcd6710aa984104e979a5c930f44561b4 (diff) | |
ice: Use PSM clock frequency to calculate RL profiles
The core clock frequency is currently hardcoded at 446 MHz for the RL
profile calculations. This causes issues since not all devices use that
clock frequency. Read the GLGEN_CLKSTAT_SRC register to determine which PSM
clock frequency is selected. This ensures that the rate limiter profile
calculations will be correct.
Signed-off-by: Ben Shelton <benjamin.h.shelton@intel.com>
Tested-by: Tony Brelinski <tonyx.brelinski@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/ice/ice_type.h')
| -rw-r--r-- | drivers/net/ethernet/intel/ice/ice_type.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/ice/ice_type.h b/drivers/net/ethernet/intel/ice/ice_type.h index 45f735d6ab72..91b7b9d1bc7f 100644 --- a/drivers/net/ethernet/intel/ice/ice_type.h +++ b/drivers/net/ethernet/intel/ice/ice_type.h @@ -618,6 +618,8 @@ struct ice_hw { void *back; struct ice_aqc_layer_props *layer_info; struct ice_port_info *port_info; + /* PSM clock frequency for calculating RL profile params */ + u32 psm_clk_freq; u64 debug_mask; /* bitmap for debug mask */ enum ice_mac_type mac_type; |