diff options
| author | Alexander Duyck <alexander.h.duyck@intel.com> | 2012-06-22 06:46:33 +0000 |
|---|---|---|
| committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2012-07-17 18:56:50 -0700 |
| commit | 4ae63730bb420610cb99ed152d6daa35236cc9e9 (patch) | |
| tree | e99f652b8840d68ca9b0499c8cffd2ad0d7ad1fe /drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | |
| parent | ac802f5dfe56139a288df50c89c820412863cd8a (diff) | |
ixgbe: Update the logic for ixgbe_cache_ring_dcb and DCB RSS configuration
This change cleans up some of the logic in an attempt to try and simplify
things for how we are configuring DCB w/ RSS.
In this patch I basically did 3 things. I updated the logic for getting
the first register index. I applied the fact that all TCs get the same
number of queues to simplify the looping logic in caching the DCB ring
register. Finally I updated how we configure the RQTC register to match
the fact that all TCs are assigned the same number of queues.
Cc: John Fastabend <john.r.fastabend@intel.com>
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/ixgbe/ixgbe_main.c')
| -rw-r--r-- | drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c index 7f2aa220501e..32c8cd649cb0 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c @@ -3608,20 +3608,16 @@ static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) /* Enable RSS Hash per TC */ if (hw->mac.type != ixgbe_mac_82598EB) { - int i; - u32 reg = 0; - u8 msb = 0; - u8 rss_i = adapter->netdev->tc_to_txq[0].count - 1; + u32 msb = 0; + u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; while (rss_i) { msb++; rss_i >>= 1; } - for (i = 0; i < MAX_TRAFFIC_CLASS; i++) - reg |= msb << IXGBE_RQTC_SHIFT_TC(i); - - IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg); + /* write msb to all 8 TCs in one write */ + IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); } } #endif |