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authorRussell King (Oracle) <rmk+kernel@armlinux.org.uk>2023-05-31 17:17:11 +0100
committerRussell King (Oracle) <rmk+kernel@armlinux.org.uk>2024-04-16 16:51:02 +0100
commit75422754ca42d76e398285c50d5182c6a9c2bad2 (patch)
tree8d6fb5b5d7d9cf62ecfe9c74cf8af28bd60ccdef /drivers/net/ethernet/marvell/mvpp2/mvpp2.h
parent3c340a0c24c8a106e03ac5f3d87b30b9cb2adc22 (diff)
net: mvpp2: add EEE implementation
Add EEE support for mvpp2, using phylink's EEE implementation, which means we just need to implement the two methods for LPI control, and with the initial configuration. Only the GMAC is supported, so only 100M, 1G and 2.5G speeds. Disabling LPI requires clearing a single bit. Enabling LPI needs a full configuration of several values, as the timer values are dependent on the MAC operating speed. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'drivers/net/ethernet/marvell/mvpp2/mvpp2.h')
-rw-r--r--drivers/net/ethernet/marvell/mvpp2/mvpp2.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index e809f91c08fb..299b996ac5df 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -481,6 +481,11 @@
#define MVPP22_GMAC_INT_SUM_MASK 0xa4
#define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1)
#define MVPP22_GMAC_INT_SUM_MASK_PTP BIT(2)
+#define MVPP2_GMAC_LPI_CTRL0 0xc0
+#define MVPP2_GMAC_LPI_CTRL0_TS_MASK GENMASK(8, 8)
+#define MVPP2_GMAC_LPI_CTRL1 0xc4
+#define MVPP2_GMAC_LPI_CTRL1_REQ_EN BIT(0)
+#define MVPP2_GMAC_LPI_CTRL1_TW_MASK GENMASK(15, 4)
/* Per-port XGMAC registers. PPv2.2 and PPv2.3, only for GOP port 0,
* relative to port->base.