diff options
| author | Russell King <rmk+kernel@armlinux.org.uk> | 2020-07-30 22:51:55 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@armlinux.org.uk> | 2020-09-09 20:47:54 +0100 |
| commit | 29edd45f604e142ed7a55cf2b376d500db2d83e9 (patch) | |
| tree | 787510237719cd5826e6f3450bfc345108f3e90b /drivers/net/ethernet/marvell/mvpp2/mvpp2.h | |
| parent | 03260b5a80fb5ca10fb7bd9b0943e10aa71949a3 (diff) | |
net: mvpp2: ptp: add support for receive timestamping
Add support for receive timestamping. When enabled, the hardware adds
a timestamp into the receive queue descriptor for all received packets
with no filtering. Hence, we can only support NONE or ALL receive
filter modes.
The timestamp in the receive queue contains two bit sof seconds and
the full nanosecond timestamp. This has to be merged with the remainder
of the seconds from the TAI clock to arrive at a full timestamp before
we can convert it to a ktime for the skb hardware timestamp field.
Acked-by: Richard Cochran <richardcochran@gmail.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'drivers/net/ethernet/marvell/mvpp2/mvpp2.h')
| -rw-r--r-- | drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 31 |
1 files changed, 30 insertions, 1 deletions
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h index 3e85cd1f9f3a..d35123237720 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h @@ -587,6 +587,9 @@ #define MVPP22_PTP_INT_CAUSE 0x00 #define MVPP22_PTP_INT_MASK 0x04 #define MVPP22_PTP_GCR 0x08 +#define MVPP22_PTP_GCR_RX_RESET BIT(13) +#define MVPP22_PTP_GCR_TX_RESET BIT(1) +#define MVPP22_PTP_GCR_TSU_ENABLE BIT(0) #define MVPP22_PTP_TX_Q0_R0 0x0c #define MVPP22_PTP_TX_Q0_R1 0x10 #define MVPP22_PTP_TX_Q0_R2 0x14 @@ -1064,6 +1067,9 @@ struct mvpp2_port { * them from 0 */ int rss_ctx[MVPP22_N_RSS_TABLES]; + + bool hwtstamp; + bool rx_hwtstamp; }; /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the @@ -1143,7 +1149,7 @@ struct mvpp22_rx_desc { __le16 reserved1; __le16 data_size; __le32 reserved2; - __le32 reserved3; + __le32 timestamp; __le64 buf_dma_addr_key_hash; __le64 buf_cookie_misc; }; @@ -1310,11 +1316,34 @@ void mvpp2_dbgfs_cleanup(struct mvpp2 *priv); #ifdef CONFIG_MVPP2_PTP int mvpp22_tai_probe(struct device *dev, struct mvpp2 *priv); +void mvpp22_tai_tstamp(struct mvpp2_tai *tai, u32 tstamp, + struct skb_shared_hwtstamps *hwtstamp); +void mvpp22_tai_start(struct mvpp2_tai *tai); +void mvpp22_tai_stop(struct mvpp2_tai *tai); +int mvpp22_tai_ptp_clock_index(struct mvpp2_tai *tai); #else static inline int mvpp22_tai_probe(struct device *dev, struct mvpp2 *priv) { return 0; } +static inline void mvpp22_tai_tstamp(struct mvpp2_tai *tai, u32 tstamp, + struct skb_shared_hwtstamps *hwtstamp) +{ +} +static inline void mvpp22_tai_start(struct mvpp2_tai *tai) +{ +} +static inline void mvpp22_tai_stop(struct mvpp2_tai *tai) +{ +} +static inline int mvpp22_tai_ptp_clock_index(struct mvpp2_tai *tai) +{ + return -1; +} #endif +static inline bool mvpp22_rx_hwtstamping(struct mvpp2_port *port) +{ + return IS_ENABLED(CONFIG_MVPP2_PTP) && port->rx_hwtstamp; +} #endif |