diff options
| author | Naveen Mamindlapalli <naveenm@marvell.com> | 2022-02-21 12:15:07 +0530 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2022-02-21 13:07:48 +0000 |
| commit | 74c1b2338e0e6fa2b84abbdf6bf0e4d5113b6eea (patch) | |
| tree | 3e31832cad08f19e22fb5f366702d8f2c94cb7cd /drivers/net/ethernet/marvell/octeontx2/af/ptp.h | |
| parent | 76ef6b80580979e125cda599d6cf0bb7a056550e (diff) | |
octeontx2-pf: cn10k: add support for new ptp timestamp format
The cn10k hardware ptp timestamp format has been modified primarily
to support 1-step ptp clock. The 64-bit timestamp used by hardware is
split into two 32-bit fields, the upper one holds seconds, the lower
one nanoseconds. A new register (PTP_CLOCK_SEC) has been added that
returns the current seconds value. The nanoseconds register PTP_CLOCK_HI
resets after every second. The cn10k RPM block provides Rx/Tx timestamps
to the NIX block using the new timestamp format. The software can read
the current timestamp in nanoseconds by reading both PTP_CLOCK_SEC &
PTP_CLOCK_HI registers.
This patch provides support for new timestamp format.
Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com>
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: Rakesh Babu Saladi <rsaladi2@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell/octeontx2/af/ptp.h')
| -rw-r--r-- | drivers/net/ethernet/marvell/octeontx2/af/ptp.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/ptp.h b/drivers/net/ethernet/marvell/octeontx2/af/ptp.h index 1b81a0493cd3..95a955159f40 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/ptp.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/ptp.h @@ -15,6 +15,8 @@ struct ptp { struct pci_dev *pdev; void __iomem *reg_base; + u64 (*read_ptp_tstmp)(struct ptp *ptp); + spinlock_t ptp_lock; /* lock */ u32 clock_rate; }; |