diff options
| author | Daniel Jurgens <danielj@mellanox.com> | 2018-11-05 16:05:37 -0600 |
|---|---|---|
| committer | Saeed Mahameed <saeedm@mellanox.com> | 2018-12-11 14:52:20 -0800 |
| commit | 939de57d30344ce728b0de61be87984e75af420e (patch) | |
| tree | dc42835752a817f639508f23b45b1601fd644861 /drivers/net/ethernet/mellanox/mlx5/core/en_main.c | |
| parent | 8c4dc42bf6e4ffeda49cf5e26bfc991b548fc0aa (diff) | |
net/mlx5e: Use CQE padding for Ethernet CQs
Writing 64B CQEs to 128B cache lines results in a RMW operation. Padding
the CQEs to 128B if possible improves performance on 128B cache line
systems like PPC.
Testing on PPC showed up to a 24% improvement in small packet throughput
vs the default behavior, depending on the workload and system topology.
Signed-off-by: Daniel Jurgens <danielj@mellanox.com>
Reviewed-by: Tariq Toukan <tariqt@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/en_main.c')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index 88116a4750b0..2188e5ba908f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -2224,6 +2224,8 @@ static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv, void *cqc = param->cqc; MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index); + if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128) + MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD); } static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, |