diff options
| author | Yevgeny Kliteynik <kliteyn@nvidia.com> | 2021-11-08 02:42:50 +0200 |
|---|---|---|
| committer | Saeed Mahameed <saeedm@nvidia.com> | 2021-12-31 00:17:34 -0800 |
| commit | f59464e257bdbd4df6df9a4505d7858a0baf6cf7 (patch) | |
| tree | 4241d823e573c61e2d4b0930fb177a7c0279629d /drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h | |
| parent | 09753babaf464177b5998c7ebb25d495c4811833 (diff) | |
net/mlx5: DR, Add support for matching on geneve_tlv_option_0_exist field
Match on geneve_tlv_option_0_exist field on devices that support STEv1.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h index 5805e2554a59..21a9b07ba327 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h @@ -442,6 +442,11 @@ void mlx5dr_ste_build_tnl_geneve_tlv_opt(struct mlx5dr_ste_ctx *ste_ctx, struct mlx5dr_match_param *mask, struct mlx5dr_cmd_caps *caps, bool inner, bool rx); +void mlx5dr_ste_build_tnl_geneve_tlv_opt_exist(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask, + struct mlx5dr_cmd_caps *caps, + bool inner, bool rx); void mlx5dr_ste_build_tnl_gtpu(struct mlx5dr_ste_ctx *ste_ctx, struct mlx5dr_ste_build *sb, struct mlx5dr_match_param *mask, @@ -666,7 +671,8 @@ struct mlx5dr_match_misc { u32 reserved_auto3:8; u32 geneve_vni:24; /* GENEVE VNI field (outer) */ - u32 reserved_auto4:7; + u32 reserved_auto4:6; + u32 geneve_tlv_option_0_exist:1; u32 geneve_oam:1; /* GENEVE OAM field (outer) */ u32 reserved_auto5:12; @@ -842,6 +848,7 @@ struct mlx5dr_cmd_caps { u8 flex_parser_id_gtpu_teid; u8 flex_parser_id_gtpu_dw_2; u8 flex_parser_id_gtpu_first_ext_dw_0; + u8 flex_parser_ok_bits_supp; u8 max_ft_level; u16 roce_min_src_udp; u8 sw_format_ver; |