diff options
| author | Yevgeny Kliteynik <kliteyn@nvidia.com> | 2022-11-15 00:11:38 +0200 |
|---|---|---|
| committer | Saeed Mahameed <saeedm@nvidia.com> | 2023-04-14 15:06:21 -0700 |
| commit | 17dc71c336aac381f59ba541cf85fb0c192d1c1c (patch) | |
| tree | 0dfaae438fbbd93d78da138aa7038cde3ddd93f6 /drivers/net/ethernet/mellanox/mlx5/core/steering | |
| parent | 7d7c9453d679fe55d72d63bacb3b639cd963ebc0 (diff) | |
net/mlx5: DR, Fix QP continuous allocation
When allocating a QP we allocate an RQ and an SQ, the RQ is stored first
in memory and followed by the SQ.
This allocation is not physically continiuos - it may span across different
physical pages. SW Steering code always writes in pairs: 1BB write + 1BB read,
or 2 continuous BBs of GTA WQE.
This lead to an issue where RQ allocation was 4x16 which is equal to 1 WQE BB,
causing 1 BB offset in the page and splitting the GTA WQE between different
physical pages.
The solution was to create the RQ with a even number of BBs and to have the
RQ aligned to a page.
Signed-off-by: Alex Vesker <valex@nvidia.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/steering')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c index d052d469d4df..4a5ae86e2b62 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c @@ -267,7 +267,7 @@ static struct mlx5dr_qp *dr_create_rc_qp(struct mlx5_core_dev *mdev, dr_qp->rq.pc = 0; dr_qp->rq.cc = 0; - dr_qp->rq.wqe_cnt = 4; + dr_qp->rq.wqe_cnt = 256; dr_qp->sq.pc = 0; dr_qp->sq.cc = 0; dr_qp->sq.head = 0; |