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authorYevgeny Kliteynik <kliteyn@nvidia.com>2023-03-01 00:16:34 +0200
committerSaeed Mahameed <saeedm@nvidia.com>2023-04-11 20:57:37 -0700
commitcee6484eddc1066f009cc82ad12a1739892172b8 (patch)
tree25ad33f942a9efa6efa91f06fa6bf216ee5c352b /drivers/net/ethernet/mellanox/mlx5/core/steering
parent9df839a711aee437390b16ee39cf0b5c1620be6a (diff)
net/mlx5: DR, Set counter ID on the last STE for STEv1 TX
In STEv1 counter action can be set either by filling counter ID on STE, in which case it is executed before other actions on this STE, or as a single action, in which case it is executed in accordance with the actions order. FW steering on STEv1 devices implements counter as counter ID on STE, and this counter is set on the last STE. Fix SMFS to be consistent with this behaviour - move TX counter to the last STE, this way the counter will include all actions of the previous STEs that might have changed packet headers length, e.g. encap, vlan push, etc. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/steering')
-rw-r--r--drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c
index 084145f18084..27cc6931bbde 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c
@@ -604,9 +604,6 @@ void dr_ste_v1_set_actions_tx(struct mlx5dr_domain *dmn,
allow_modify_hdr = false;
}
- if (action_type_set[DR_ACTION_TYP_CTR])
- dr_ste_v1_set_counter_id(last_ste, attr->ctr_id);
-
if (action_type_set[DR_ACTION_TYP_MODIFY_HDR]) {
if (!allow_modify_hdr || action_sz < DR_STE_ACTION_DOUBLE_SZ) {
dr_ste_v1_arr_init_next_match(&last_ste, added_stes,
@@ -724,6 +721,10 @@ void dr_ste_v1_set_actions_tx(struct mlx5dr_domain *dmn,
attr->range.max);
}
+ /* set counter ID on the last STE to adhere to DMFS behavior */
+ if (action_type_set[DR_ACTION_TYP_CTR])
+ dr_ste_v1_set_counter_id(last_ste, attr->ctr_id);
+
dr_ste_v1_set_hit_gvmi(last_ste, attr->hit_gvmi);
dr_ste_v1_set_hit_addr(last_ste, attr->final_icm_addr, 1);
}