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authorDanielle Ratson <danieller@nvidia.com>2022-07-27 09:23:21 +0300
committerDavid S. Miller <davem@davemloft.net>2022-07-29 11:02:23 +0100
commit42823208b946d85d20a7065a1b2ef6e35a7be3a9 (patch)
treea0ddb469540b07b95840f291c8775b074948f18a /drivers/net/ethernet/mellanox/mlxsw/core.h
parent37b62b282b182acd2113f97c1b9fd651d4211027 (diff)
mlxsw: Support CQEv2 for SDQ in Spectrum-2 and newer ASICs
Currently, Tx completions are reported using Completion Queue Element version 1 (CQEv1). These elements do not contain the Tx time stamp, which is fine as Spectrum-1 reads Tx time stamps via a dedicated FIFO and Spectrum-2 does not currently support PTP. In preparation for Spectrum-2 PTP support, use CQEv2 for Spectrum-2 and newer ASICs, as this CQE format encodes the Tx time stamp. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlxsw/core.h')
-rw-r--r--drivers/net/ethernet/mellanox/mlxsw/core.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.h b/drivers/net/ethernet/mellanox/mlxsw/core.h
index 7213e4528298..6c332bb9b6eb 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/core.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/core.h
@@ -427,6 +427,7 @@ struct mlxsw_driver {
u8 txhdr_len;
const struct mlxsw_config_profile *profile;
+ bool sdq_supports_cqe_v2;
};
int mlxsw_core_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
@@ -437,6 +438,8 @@ int mlxsw_core_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
u32 mlxsw_core_read_frc_h(struct mlxsw_core *mlxsw_core);
u32 mlxsw_core_read_frc_l(struct mlxsw_core *mlxsw_core);
+bool mlxsw_core_sdq_supports_cqe_v2(struct mlxsw_core *mlxsw_core);
+
void mlxsw_core_emad_string_tlv_enable(struct mlxsw_core *mlxsw_core);
bool mlxsw_core_res_valid(struct mlxsw_core *mlxsw_core,