diff options
| author | Petr Machata <petrm@mellanox.com> | 2018-07-27 15:27:00 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2018-07-27 13:17:50 -0700 |
| commit | 55fb71f481aac930ba87dc0f99a3060ced0326d3 (patch) | |
| tree | 0d1415c1b87f41224412d50f7bf196dca36790de /drivers/net/ethernet/mellanox/mlxsw/spectrum_dcb.c | |
| parent | e67131d9b861eb753b077961e291fc21a59daa28 (diff) | |
mlxsw: reg: Add QoS Priority to DSCP Mapping Register
This register controls mapping from Priority to DSCP for purposes of
rewrite. Note that rewrite happens as the packet is transmitted provided
that the DSCP rewrite bit is enabled for the packet.
Signed-off-by: Petr Machata <petrm@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlxsw/spectrum_dcb.c')
0 files changed, 0 insertions, 0 deletions