diff options
| author | Jiri Pirko <jiri@nvidia.com> | 2020-11-10 11:48:47 +0200 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2020-11-12 15:55:19 -0800 |
| commit | d57ff022866660a66bcb6b10f1f114fd5521c3df (patch) | |
| tree | 05c5afe46a21394b86b989823cc885ca93e1b8f2 /drivers/net/ethernet/mellanox/mlxsw/spectrum_ipip.c | |
| parent | 69ba53e72bbd7cbd7410136ba9dc04adf8a3f91a (diff) | |
mlxsw: spectrum_router: Use RALUE-independent op arg
Since the write/delete of FIB entry is going to be implemented by XMDR
register for XM implementation, introduce RALUE-independent enum for op
so the enum could be used in both RALUE and XMDR.
Signed-off-by: Jiri Pirko <jiri@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlxsw/spectrum_ipip.c')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlxsw/spectrum_ipip.c | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_ipip.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_ipip.c index a8525992528f..8487de3e9787 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_ipip.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_ipip.c @@ -183,12 +183,25 @@ mlxsw_sp_ipip_fib_entry_op_gre4_rtdp(struct mlxsw_sp *mlxsw_sp, static int mlxsw_sp_ipip_fib_entry_op_gre4_ralue(struct mlxsw_sp *mlxsw_sp, u32 dip, u8 prefix_len, u16 ul_vr_id, - enum mlxsw_reg_ralue_op op, + enum mlxsw_sp_fib_entry_op op, u32 tunnel_index) { char ralue_pl[MLXSW_REG_RALUE_LEN]; + enum mlxsw_reg_ralue_op ralue_op; + + switch (op) { + case MLXSW_SP_FIB_ENTRY_OP_WRITE: + ralue_op = MLXSW_REG_RALUE_OP_WRITE_WRITE; + break; + case MLXSW_SP_FIB_ENTRY_OP_DELETE: + ralue_op = MLXSW_REG_RALUE_OP_WRITE_DELETE; + break; + default: + WARN_ON_ONCE(1); + return -EINVAL; + } - mlxsw_reg_ralue_pack4(ralue_pl, MLXSW_REG_RALXX_PROTOCOL_IPV4, op, + mlxsw_reg_ralue_pack4(ralue_pl, MLXSW_REG_RALXX_PROTOCOL_IPV4, ralue_op, ul_vr_id, prefix_len, dip); mlxsw_reg_ralue_act_ip2me_tun_pack(ralue_pl, tunnel_index); return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ralue), ralue_pl); @@ -196,7 +209,7 @@ mlxsw_sp_ipip_fib_entry_op_gre4_ralue(struct mlxsw_sp *mlxsw_sp, static int mlxsw_sp_ipip_fib_entry_op_gre4(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_ipip_entry *ipip_entry, - enum mlxsw_reg_ralue_op op, + enum mlxsw_sp_fib_entry_op op, u32 tunnel_index) { u16 ul_vr_id = mlxsw_sp_ipip_lb_ul_vr_id(ipip_entry->ol_lb); |