diff options
| author | Alexander Lobakin <alobakin@marvell.com> | 2020-07-06 18:38:19 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2020-07-06 13:18:56 -0700 |
| commit | 5ab903418ad14732131df0af0d63f19b73e377ae (patch) | |
| tree | 7a9c443c1b8a965352883cc3ad620603d6282762 /drivers/net/ethernet/qlogic/qed/qed_cxt.c | |
| parent | a0f3266f4bf966eefd02123d3aacdf7df8d67c1c (diff) | |
net: qed: sanitize BE/LE data processing
Current code assumes that both host and device operates in Little Endian
in lots of places. While this is true for x86 platform, this doesn't mean
we should not care about this.
This commit addresses all parts of the code that were pointed out by sparse
checker. All operations with restricted (__be*/__le*) types are now
protected with explicit from/to CPU conversions, even if they're noops on
common setups.
I'm sure there are more such places, but this implies a deeper code
investigation, and is a subject for future works.
Signed-off-by: Alexander Lobakin <alobakin@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/qlogic/qed/qed_cxt.c')
| -rw-r--r-- | drivers/net/ethernet/qlogic/qed/qed_cxt.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/drivers/net/ethernet/qlogic/qed/qed_cxt.c b/drivers/net/ethernet/qlogic/qed/qed_cxt.c index 3a62358b9749..5362dc18b6c2 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_cxt.c +++ b/drivers/net/ethernet/qlogic/qed/qed_cxt.c @@ -73,8 +73,8 @@ union type1_task_context { }; struct src_ent { - u8 opaque[56]; - u64 next; + __u8 opaque[56]; + __be64 next; }; #define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */ @@ -2177,6 +2177,7 @@ qed_cxt_dynamic_ilt_alloc(struct qed_hwfn *p_hwfn, dma_addr_t p_phys; u64 ilt_hw_entry; void *p_virt; + u32 flags1; int rc = 0; switch (elem_type) { @@ -2255,8 +2256,10 @@ qed_cxt_dynamic_ilt_alloc(struct qed_hwfn *p_hwfn, elem = (union type1_task_context *)elem_start; tdif_context = &elem->roce_ctx.tdif_context; - SET_FIELD(tdif_context->flags1, - TDIF_TASK_CONTEXT_REF_TAG_MASK, 0xf); + flags1 = le32_to_cpu(tdif_context->flags1); + SET_FIELD(flags1, TDIF_TASK_CONTEXT_REF_TAG_MASK, 0xf); + tdif_context->flags1 = cpu_to_le32(flags1); + elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn); } } |