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author | Russell King <rmk+kernel@armlinux.org.uk> | 2017-09-24 11:32:52 +0100 |
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committer | Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2025-01-20 12:24:15 +0000 |
commit | de03295bbefa193eaa163c735f63548129c4de9d (patch) | |
tree | de3e1ebc56ac68cabba8f86468da227d243b8242 /drivers/net/ethernet/sfc/ef100_sriov.c | |
parent | 1760d29900e582610f24d8f00e618a3777e89dc4 (diff) |
rtc: pcf8523: provide set_offset_nsec
When we set the time, we set the STOP bit, set the time, and then clear
the STOP bit. Concerning the timing, the PCF8523 data sheet says:
"The first increment of the time circuits is between 0.499878s and
0.500000s after STOP is released."
However, practical measurement shows this is not the case - with the I2C
bus speed at 100kHz on iMX6, it takes about 5ms for the rtclib call for
setting the time to complete. However, reading back when the second
actually flips shows that there's an additional 10ms which can't be
accounted for by the read - a read of the RTC takes 1.7 to 1.8 ms.
Practical measurement shows that the first increment occurs about 515ms
after the write, which means we need to set the current second 485ms
after it has started.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'drivers/net/ethernet/sfc/ef100_sriov.c')
0 files changed, 0 insertions, 0 deletions