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authorRussell King (Oracle) <rmk+kernel@armlinux.org.uk>2022-01-18 10:18:55 +0000
committerRussell King (Oracle) <rmk+kernel@armlinux.org.uk>2022-01-18 10:18:55 +0000
commit51efd61e20a08e1a262c3b8b6219600ebca2006c (patch)
tree887b7604bffd071d5a07640040cc8c9d7f7b09a6 /drivers/net/ethernet/xilinx/xilinx_axienet.h
parent956c86b60ce352b3e195c6f0700a07176989d356 (diff)
parente2365fc3e4a0e134ee7f875ce71f0abaaeb4552d (diff)
Merge branches 'mvebu-cpuidle' and 'mvneta' into clearfog
Diffstat (limited to 'drivers/net/ethernet/xilinx/xilinx_axienet.h')
-rw-r--r--drivers/net/ethernet/xilinx/xilinx_axienet.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h
index 5b4d153b1492..40108968b350 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet.h
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h
@@ -386,6 +386,7 @@ struct axidma_bd {
* @phylink: Pointer to phylink instance
* @phylink_config: phylink configuration settings
* @pcs_phy: Reference to PCS/PMA PHY if used
+ * @pcs: phylink pcs structure for PCS PHY
* @switch_x_sgmii: Whether switchable 1000BaseX/SGMII mode is enabled in the core
* @axi_clk: AXI4-Lite bus clock
* @misc_clks: Misc ethernet clocks (AXI4-Stream, Ref, MGT clocks)
@@ -434,6 +435,7 @@ struct axienet_local {
struct phylink_config phylink_config;
struct mdio_device *pcs_phy;
+ struct phylink_pcs pcs;
bool switch_x_sgmii;