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authorRussell King (Oracle) <rmk+kernel@armlinux.org.uk>2021-11-23 17:57:08 +0000
committerRussell King (Oracle) <rmk+kernel@armlinux.org.uk>2022-01-12 11:07:36 +0000
commitde659a7d491239c172808e056320c0c5aeacee26 (patch)
treea99908c9e58eb6744fe62c58904edc224a488a9b /drivers/net/ethernet/xilinx/xilinx_axienet.h
parentbae390b5e5a0a6d569d0f963955d5570814c7382 (diff)
net: axienet: convert to phylink_pcs
Convert axienet to use the phylink_pcs layer, resulting in it no longer being a legacy driver. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'drivers/net/ethernet/xilinx/xilinx_axienet.h')
-rw-r--r--drivers/net/ethernet/xilinx/xilinx_axienet.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h
index 5b4d153b1492..40108968b350 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet.h
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h
@@ -386,6 +386,7 @@ struct axidma_bd {
* @phylink: Pointer to phylink instance
* @phylink_config: phylink configuration settings
* @pcs_phy: Reference to PCS/PMA PHY if used
+ * @pcs: phylink pcs structure for PCS PHY
* @switch_x_sgmii: Whether switchable 1000BaseX/SGMII mode is enabled in the core
* @axi_clk: AXI4-Lite bus clock
* @misc_clks: Misc ethernet clocks (AXI4-Stream, Ref, MGT clocks)
@@ -434,6 +435,7 @@ struct axienet_local {
struct phylink_config phylink_config;
struct mdio_device *pcs_phy;
+ struct phylink_pcs pcs;
bool switch_x_sgmii;