diff options
| author | Alex Elder <elder@linaro.org> | 2022-09-26 17:09:27 -0500 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2022-09-27 18:42:51 -0700 |
| commit | 9265a4f0f0b4bdcebeb3ca4688e8213bdadaa759 (patch) | |
| tree | c59323418de684a4ba5109d359863d556f471cb6 /drivers/net/ipa/ipa_main.c | |
| parent | b5c35fa470ecbfeeb7a8caf1ff4d739a6bafcd4a (diff) | |
net: ipa: define even more IPA register fields
Define the fields for the FLAVOR_0, IDLE_INDICATION_CFG,
QTIME_TIMESTAMP_CFG, TIMERS_XO_CLK_DIV_CFG and TIMERS_PULSE_GRAN_CFG
IPA registers for all supported IPA versions.
Create enumerated types to identify fields for these IPA registers.
Use IPA_REG_FIELDS() to specify the field mask values defined for
these registers, for each supported version of IPA.
Use ipa_reg_bit() and ipa_reg_encode() to build up the values to be
written to these registers. Use ipa_reg_decode() to extract field
values from the FLAVOR_0 register.
Remove the definition of the no-longer-used *_FMASK symbols.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/net/ipa/ipa_main.c')
| -rw-r--r-- | drivers/net/ipa/ipa_main.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c index 23ab566b71dd..a0f6212aa3c3 100644 --- a/drivers/net/ipa/ipa_main.c +++ b/drivers/net/ipa/ipa_main.c @@ -361,31 +361,31 @@ static void ipa_qtime_config(struct ipa *ipa) reg = ipa_reg(ipa, QTIME_TIMESTAMP_CFG); /* Set DPL time stamp resolution to use Qtime (instead of 1 msec) */ - val = u32_encode_bits(DPL_TIMESTAMP_SHIFT, DPL_TIMESTAMP_LSB_FMASK); - val |= u32_encode_bits(1, DPL_TIMESTAMP_SEL_FMASK); + val = ipa_reg_encode(reg, DPL_TIMESTAMP_LSB, DPL_TIMESTAMP_SHIFT); + val |= ipa_reg_bit(reg, DPL_TIMESTAMP_SEL); /* Configure tag and NAT Qtime timestamp resolution as well */ - val |= u32_encode_bits(TAG_TIMESTAMP_SHIFT, TAG_TIMESTAMP_LSB_FMASK); - val |= u32_encode_bits(NAT_TIMESTAMP_SHIFT, NAT_TIMESTAMP_LSB_FMASK); + val = ipa_reg_encode(reg, TAG_TIMESTAMP_LSB, TAG_TIMESTAMP_SHIFT); + val = ipa_reg_encode(reg, NAT_TIMESTAMP_LSB, NAT_TIMESTAMP_SHIFT); iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); /* Set granularity of pulse generators used for other timers */ reg = ipa_reg(ipa, TIMERS_PULSE_GRAN_CFG); - val = u32_encode_bits(IPA_GRAN_100_US, GRAN_0_FMASK); - val |= u32_encode_bits(IPA_GRAN_1_MS, GRAN_1_FMASK); - val |= u32_encode_bits(IPA_GRAN_1_MS, GRAN_2_FMASK); + val = ipa_reg_encode(reg, PULSE_GRAN_0, IPA_GRAN_100_US); + val |= ipa_reg_encode(reg, PULSE_GRAN_1, IPA_GRAN_1_MS); + val |= ipa_reg_encode(reg, PULSE_GRAN_2, IPA_GRAN_1_MS); iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); /* Actual divider is 1 more than value supplied here */ reg = ipa_reg(ipa, TIMERS_XO_CLK_DIV_CFG); offset = ipa_reg_offset(reg); - val = u32_encode_bits(IPA_XO_CLOCK_DIVIDER - 1, DIV_VALUE_FMASK); + val = ipa_reg_encode(reg, DIV_VALUE, IPA_XO_CLOCK_DIVIDER - 1); iowrite32(val, ipa->reg_virt + offset); /* Divider value is set; re-enable the common timer clock divider */ - val |= u32_encode_bits(1, DIV_ENABLE_FMASK); + val |= ipa_reg_bit(reg, DIV_ENABLE); iowrite32(val, ipa->reg_virt + offset); } @@ -435,10 +435,10 @@ static void ipa_idle_indication_cfg(struct ipa *ipa, u32 val; reg = ipa_reg(ipa, IDLE_INDICATION_CFG); - val = u32_encode_bits(enter_idle_debounce_thresh, - ENTER_IDLE_DEBOUNCE_THRESH_FMASK); + val = ipa_reg_encode(reg, ENTER_IDLE_DEBOUNCE_THRESH, + enter_idle_debounce_thresh); if (const_non_idle_enable) - val |= CONST_NON_IDLE_ENABLE_FMASK; + val |= ipa_reg_bit(reg, CONST_NON_IDLE_ENABLE); iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg)); } |