diff options
| author | Alex Elder <elder@linaro.org> | 2021-03-25 09:44:33 -0500 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-03-25 17:22:30 -0700 |
| commit | cc5199ed50f2939743185fac94f1bcb47200684a (patch) | |
| tree | 8ec391f7257cead9498a47683cfd31c37047ac27 /drivers/net/ipa/ipa_reg.h | |
| parent | b8ecdaaaf328cf2914da99217368dc847fb9e968 (diff) | |
net: ipa: update component config register
IPA version 4.9 and later use a different layout of some fields
found in the COMP_CFG register.
Define arbitration_lock_disable_encoded(), and use it to encode a
value into the ATOMIC_FETCHER_ARB_LOCK_DIS field based on the IPA
version.
And define full_flush_rsc_closure_en_encoded() to encode a value
into the FULL_FLUSH_WAIT_RSC_CLOSE_EN field based on the IPA
version.
The values of these fields are neither modified nor extracted by
current code, but this patch makes this possible for all supported
versions.
Fix a mistaken comment above ipa_hardware_config_comp() intended to
describe the purpose for the register.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ipa/ipa_reg.h')
| -rw-r--r-- | drivers/net/ipa/ipa_reg.h | 32 |
1 files changed, 29 insertions, 3 deletions
diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h index 735f6e809e04..8a654ccda49e 100644 --- a/drivers/net/ipa/ipa_reg.h +++ b/drivers/net/ipa/ipa_reg.h @@ -88,9 +88,6 @@ struct ipa; #define GSI_SNOC_CNOC_LOOP_PROT_DISABLE_FMASK GENMASK(14, 14) #define GSI_MULTI_AXI_MASTERS_DIS_FMASK GENMASK(15, 15) #define IPA_QMB_SELECT_GLOBAL_EN_FMASK GENMASK(16, 16) -#define IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_FMASK GENMASK(20, 17) -/* The next field is present for IPA v4.5 and IPA v4.7 */ -#define IPA_FULL_FLUSH_WAIT_RSC_CLOSE_EN_FMASK GENMASK(21, 21) /* The next five fields are present for IPA v4.9+ */ #define QMB_RAM_RD_CACHE_DISABLE_FMASK GENMASK(19, 19) #define GENQMB_AOOOWR_FMASK GENMASK(20, 20) @@ -98,6 +95,35 @@ struct ipa; #define GEN_QMB_1_DYNAMIC_ASIZE_FMASK GENMASK(30, 30) #define GEN_QMB_0_DYNAMIC_ASIZE_FMASK GENMASK(31, 31) +/* Encoded value for COMP_CFG register ATOMIC_FETCHER_ARB_LOCK_DIS field */ +static inline u32 arbitration_lock_disable_encoded(enum ipa_version version, + u32 mask) +{ + /* assert(version >= IPA_VERSION_4_0); */ + + if (version < IPA_VERSION_4_9) + return u32_encode_bits(mask, GENMASK(20, 17)); + + if (version == IPA_VERSION_4_9) + return u32_encode_bits(mask, GENMASK(24, 22)); + + return u32_encode_bits(mask, GENMASK(23, 22)); +} + +/* Encoded value for COMP_CFG register FULL_FLUSH_WAIT_RS_CLOSURE_EN field */ +static inline u32 full_flush_rsc_closure_en_encoded(enum ipa_version version, + bool enable) +{ + u32 val = enable ? 1 : 0; + + /* assert(version >= IPA_VERSION_4_5); */ + + if (version == IPA_VERSION_4_5 || version == IPA_VERSION_4_7) + return u32_encode_bits(val, GENMASK(21, 21)); + + return u32_encode_bits(val, GENMASK(17, 17)); +} + #define IPA_REG_CLKON_CFG_OFFSET 0x00000044 #define RX_FMASK GENMASK(0, 0) #define PROC_FMASK GENMASK(1, 1) |