diff options
| author | Zheng Yongjun <zhengyongjun3@huawei.com> | 2021-06-01 22:18:59 +0800 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-06-01 17:05:05 -0700 |
| commit | e65c27938d8e3dd67d55049a82f27e56ca31e728 (patch) | |
| tree | 3b38f47615ca72168f97ab0bab55b27f71d2e761 /drivers/net/mdio/mdio-mux-meson-g12a.c | |
| parent | f62c4f3870d8114029d3ebfc7ec4421728f07f83 (diff) | |
net: mdio: Fix spelling mistakes
informations ==> information
typicaly ==> typically
derrive ==> derive
eventhough ==> even though
Signed-off-by: Zheng Yongjun <zhengyongjun3@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/mdio/mdio-mux-meson-g12a.c')
| -rw-r--r-- | drivers/net/mdio/mdio-mux-meson-g12a.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/mdio/mdio-mux-meson-g12a.c b/drivers/net/mdio/mdio-mux-meson-g12a.c index bf86c9c7a288..b8866bc3f2e8 100644 --- a/drivers/net/mdio/mdio-mux-meson-g12a.c +++ b/drivers/net/mdio/mdio-mux-meson-g12a.c @@ -95,7 +95,7 @@ static int g12a_ephy_pll_enable(struct clk_hw *hw) /* Poll on the digital lock instead of the usual analog lock * This is done because bit 31 is unreliable on some SoC. Bit - * 31 may indicate that the PLL is not lock eventhough the clock + * 31 may indicate that the PLL is not lock even though the clock * is actually running */ return readl_poll_timeout(pll->base + ETH_PLL_CTL0, val, |