diff options
| author | Russell King <rmk+kernel@armlinux.org.uk> | 2017-01-04 19:30:30 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@armlinux.org.uk> | 2017-02-20 10:47:20 +0000 |
| commit | c52228d4f16d0b44bb77683602cfa1df821c0ba5 (patch) | |
| tree | 5c7c79109a2a2b21aa6225ad6b7dbba30806f8bc /drivers/net/phy/bcm-phy-lib.c | |
| parent | e3b632fd8c50e2c4f6269f80d07d94e2f0d04b7b (diff) | |
net: phy: switch remaining users to phy_(read|write)_mmd()
Switch everyone over to using phy_read_mmd() and phy_write_mmd() now
that they are able to handle both Clause 22 indirect addressing and
Clause 45 direct addressing methods to the MMD registers.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'drivers/net/phy/bcm-phy-lib.c')
| -rw-r--r-- | drivers/net/phy/bcm-phy-lib.c | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/drivers/net/phy/bcm-phy-lib.c b/drivers/net/phy/bcm-phy-lib.c index ab9ad689617c..90be6ee42dfa 100644 --- a/drivers/net/phy/bcm-phy-lib.c +++ b/drivers/net/phy/bcm-phy-lib.c @@ -201,8 +201,7 @@ int bcm_phy_set_eee(struct phy_device *phydev, bool enable) int val; /* Enable EEE at PHY level */ - val = phy_read_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL, - MDIO_MMD_AN); + val = phy_read_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL); if (val < 0) return val; @@ -211,12 +210,10 @@ int bcm_phy_set_eee(struct phy_device *phydev, bool enable) else val &= ~(LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X); - phy_write_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL, - MDIO_MMD_AN, (u32)val); + phy_write_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL, (u32)val); /* Advertise EEE */ - val = phy_read_mmd_indirect(phydev, BCM_CL45VEN_EEE_ADV, - MDIO_MMD_AN); + val = phy_read_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV); if (val < 0) return val; @@ -225,8 +222,7 @@ int bcm_phy_set_eee(struct phy_device *phydev, bool enable) else val &= ~(MDIO_AN_EEE_ADV_100TX | MDIO_AN_EEE_ADV_1000T); - phy_write_mmd_indirect(phydev, BCM_CL45VEN_EEE_ADV, - MDIO_MMD_AN, (u32)val); + phy_write_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV, (u32)val); return 0; } |