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authorAntoine Tenart <antoine.tenart@bootlin.com>2020-01-13 23:31:46 +0100
committerDavid S. Miller <davem@davemloft.net>2020-01-14 11:31:41 -0800
commit28c5107aa904ef9db6b023039d20b6b4c4181675 (patch)
tree3db8247b5ec2c94504c3c82f42c00976a5625294 /drivers/net/phy/mscc_macsec.h
parent1bbe0ecc2a1a008bcfeb7fd2d8f95c8e9a1867c6 (diff)
net: phy: mscc: macsec support
This patch adds MACsec offloading support to some Microsemi PHYs, to configure flows and transformations so that matched packets can be processed by the MACsec engine, either at egress, or at ingress. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/phy/mscc_macsec.h')
-rw-r--r--drivers/net/phy/mscc_macsec.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/phy/mscc_macsec.h b/drivers/net/phy/mscc_macsec.h
index 0d108da28dad..9b5d0af91d20 100644
--- a/drivers/net/phy/mscc_macsec.h
+++ b/drivers/net/phy/mscc_macsec.h
@@ -8,6 +8,8 @@
#ifndef _MSCC_OCELOT_MACSEC_H_
#define _MSCC_OCELOT_MACSEC_H_
+#define MSCC_MS_MAX_FLOWS 16
+
#define CONTROL_TYPE_EGRESS 0x6
#define CONTROL_TYPE_INGRESS 0xf
#define CONTROL_IV0 BIT(5)
@@ -59,6 +61,8 @@ enum mscc_macsec_validate_levels {
#define MSCC_MS_XFORM_REC(x, y) (((x) << 5) + (y))
#define MSCC_MS_ENA_CFG 0x800
#define MSCC_MS_FC_CFG 0x804
+#define MSCC_MS_SAM_MAC_SA_MATCH_LO(x) (0x1000 + ((x) << 4))
+#define MSCC_MS_SAM_MAC_SA_MATCH_HI(x) (0x1001 + ((x) << 4))
#define MSCC_MS_SAM_MISC_MATCH(x) (0x1004 + ((x) << 4))
#define MSCC_MS_SAM_MATCH_SCI_LO(x) (0x1005 + ((x) << 4))
#define MSCC_MS_SAM_MATCH_SCI_HI(x) (0x1006 + ((x) << 4))