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authorRussell King <rmk+kernel@armlinux.org.uk>2017-12-29 12:46:22 +0000
committerDavid S. Miller <davem@davemloft.net>2018-01-02 15:00:49 -0500
commit05ca1b327eed2b9abb48cbd013ca451032bd86b0 (patch)
tree9165b554e1beefd7229dcbfd946201e11f1e888f /drivers/net/phy
parent3abbcccc6f318f858ffbd4e3d82839b66ff1b960 (diff)
net: phy: marvell10g: update header comments
Update header comments to indicate the newly found behaviour with XAUI interfaces. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/phy')
-rw-r--r--drivers/net/phy/marvell10g.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index f0cfba4e758b..37ba68d7c385 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -6,12 +6,18 @@
*
* There appears to be several different data paths through the PHY which
* are automatically managed by the PHY. The following has been determined
- * via observation and experimentation:
+ * via observation and experimentation for a setup using single-lane Serdes:
*
* SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
* 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
* 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
*
+ * With XAUI, observation shows:
+ *
+ * XAUI PHYXS -- <appropriate PCS as above>
+ *
+ * and no switching of the host interface mode occurs.
+ *
* If both the fiber and copper ports are connected, the first to gain
* link takes priority and the other port is completely locked out.
*/