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authorHector Palacios <hector.palacios@digi.com>2013-03-10 22:50:03 +0000
committerDavid S. Miller <davem@davemloft.net>2013-03-12 06:50:59 -0400
commitb6bb4dfcb1803765e7d12a9807a8d4650545199a (patch)
tree85ad7923c17535647cfd736a0d01b62bb642c244 /drivers/net/phy
parentb818d1a7f72575eef17e00dc4085512c9cc8897d (diff)
phy/micrel: move flag handling to function for common use
The flag MICREL_PHY_50MHZ_CLK is not of exclusive use of KSZ8051 model. At least KSZ8021 and KSZ8031 models also use it. This patch moves the handling of this and future flags to a separate function so that the different PHY models can call it on their init function, if needed. Signed-off-by: Hector Palacios <hector.palacios@digi.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/phy')
-rw-r--r--drivers/net/phy/micrel.c27
1 files changed, 18 insertions, 9 deletions
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 018af1852fe1..2510435f34ed 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -53,6 +53,18 @@
#define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14)
#define KSZ8051_RMII_50MHZ_CLK (1 << 7)
+static int ksz_config_flags(struct phy_device *phydev)
+{
+ int regval;
+
+ if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
+ regval = phy_read(phydev, MII_KSZPHY_CTRL);
+ regval |= KSZ8051_RMII_50MHZ_CLK;
+ return phy_write(phydev, MII_KSZPHY_CTRL, regval);
+ }
+ return 0;
+}
+
static int kszphy_ack_interrupt(struct phy_device *phydev)
{
/* bit[7..0] int status, which is a read and clear register. */
@@ -114,22 +126,19 @@ static int kszphy_config_init(struct phy_device *phydev)
static int ksz8021_config_init(struct phy_device *phydev)
{
+ int rc;
const u16 val = KSZPHY_OMSO_B_CAST_OFF | KSZPHY_OMSO_RMII_OVERRIDE;
phy_write(phydev, MII_KSZPHY_OMSO, val);
- return 0;
+ rc = ksz_config_flags(phydev);
+ return rc < 0 ? rc : 0;
}
static int ks8051_config_init(struct phy_device *phydev)
{
- int regval;
-
- if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
- regval = phy_read(phydev, MII_KSZPHY_CTRL);
- regval |= KSZ8051_RMII_50MHZ_CLK;
- phy_write(phydev, MII_KSZPHY_CTRL, regval);
- }
+ int rc;
- return 0;
+ rc = ksz_config_flags(phydev);
+ return rc < 0 ? rc : 0;
}
#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06