diff options
| author | Holger Brunck <holger.brunck@keymile.com> | 2017-05-17 17:24:38 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2017-05-18 10:28:39 -0400 |
| commit | 067bb938dad61e58fc3d6a0e090b72ec011851cd (patch) | |
| tree | 617e9b79f94dfe0cdff171fae024b7f13353b657 /drivers/net/wan/fsl_ucc_hdlc.h | |
| parent | c7f235a7c2d09b1b83671ba2d93ebee981554467 (diff) | |
net/wan/fsl_ucc_hdlc: add hdlc-bus support
This adds support for hdlc-bus mode to the fsl_ucc_hdlc driver. This can
be enabled with the "fsl,hdlc-bus" property in the DTS node of the
corresponding ucc.
This aligns the configuration of the UPSMR and GUMR registers to what is
done in our ucc_hdlc driver (that only support hdlc-bus mode) and with
the QuickEngine's documentation for hdlc-bus mode.
GUMR/SYNL is set to AUTO for the busmode as in this case the CD signal
is ignored. The brkpt_support is enabled to set the HBM1 bit in the
CMXUCR register to configure an open-drain connected HDLC bus.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Cc: Zhao Qiang <qiang.zhao@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/wan/fsl_ucc_hdlc.h')
| -rw-r--r-- | drivers/net/wan/fsl_ucc_hdlc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/wan/fsl_ucc_hdlc.h b/drivers/net/wan/fsl_ucc_hdlc.h index 881ecdeef076..c21134c1f180 100644 --- a/drivers/net/wan/fsl_ucc_hdlc.h +++ b/drivers/net/wan/fsl_ucc_hdlc.h @@ -78,6 +78,7 @@ struct ucc_hdlc_private { u16 tsa; bool hdlc_busy; bool loopback; + bool hdlc_bus; u8 *tx_buffer; u8 *rx_buffer; |