diff options
| author | Marek Vasut <marex@denx.de> | 2024-06-11 10:36:04 +0200 |
|---|---|---|
| committer | Paolo Abeni <pabeni@redhat.com> | 2024-06-14 10:50:56 +0200 |
| commit | cbfad55322ceee283ff1dd053725b93c86018b88 (patch) | |
| tree | f2ba5acc13f08b4be9ee90ef84e986b5bbe776e6 /drivers/net | |
| parent | c60a54b52026bd2c9a88ae00f2aac7a67fed8e38 (diff) | |
net: stmmac: dwmac-stm32: Fix Mhz to MHz
Trivial, fix up the comments using 'Mhz' to 'MHz'.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index 75981ac2cbb5..bed2be129b2d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -58,7 +58,7 @@ * Below table summarizes the clock requirement and clock sources for * supported phy interface modes. * __________________________________________________________________________ - *|PHY_MODE | Normal | PHY wo crystal| PHY wo crystal |No 125Mhz from PHY| + *|PHY_MODE | Normal | PHY wo crystal| PHY wo crystal |No 125MHz from PHY| *| | | 25MHz | 50MHz | | * --------------------------------------------------------------------------- *| MII | - | eth-ck | n/a | n/a | @@ -367,7 +367,7 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac, /* Gigabit Ethernet 125MHz clock selection. */ dwmac->eth_clk_sel_reg = of_property_read_bool(np, "st,eth-clk-sel"); - /* Ethernet 50Mhz RMII clock selection */ + /* Ethernet 50MHz RMII clock selection */ dwmac->eth_ref_clk_sel_reg = of_property_read_bool(np, "st,eth-ref-clk-sel"); |