diff options
| author | Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2022-04-07 15:52:20 +0100 |
|---|---|---|
| committer | Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2022-04-14 10:12:25 +0100 |
| commit | 748630e915d29ff5d75b73e0896429911e0ee6ba (patch) | |
| tree | ea6cb674493f84383a0825c01bdd84049dce5458 /drivers/net | |
| parent | df35e7c02bde9061db9b05efba356204fa98dc4d (diff) | |
net: mtk_eth_soc: add mask and update PCS speed definitions
The PCS speed setting is a two bit field, but it is defined as two
separate bits. Add a bitfield mask for the speed definitions, and
use the FIELD_PREP() macro to define each PCS speed.
Tested-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/ethernet/mediatek/mtk_eth_soc.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 8a10761adda0..f31ef594008a 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -17,6 +17,7 @@ #include <linux/phylink.h> #include <linux/rhashtable.h> #include <linux/dim.h> +#include <linux/bitfield.h> #include "mtk_ppe.h" #define MTK_QDMA_PAGE_SIZE 2048 @@ -485,9 +486,10 @@ #define SGMSYS_SGMII_MODE 0x20 #define SGMII_IF_MODE_BIT0 BIT(0) #define SGMII_SPEED_DUPLEX_AN BIT(1) -#define SGMII_SPEED_10 0x0 -#define SGMII_SPEED_100 BIT(2) -#define SGMII_SPEED_1000 BIT(3) +#define SGMII_SPEED_MASK GENMASK(3, 2) +#define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0) +#define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1) +#define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2) #define SGMII_DUPLEX_FULL BIT(4) #define SGMII_IF_MODE_BIT5 BIT(5) #define SGMII_REMOTE_FAULT_DIS BIT(8) |