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authorJakub Kicinski <kuba@kernel.org>2023-07-27 20:32:59 -0700
committerJakub Kicinski <kuba@kernel.org>2023-07-27 20:33:00 -0700
commit85e2a2c42b662a1040b98c67f504f8fa52c52bc0 (patch)
tree1bf390afd7dbb42563472fb223fc5b48fce7d9ca /drivers/net
parent5908a4c47c9c8d7898841dc3dd2e70aa5d91bc05 (diff)
parentdb845b9b2040f4ed5f8bce6cd30103e3b8557566 (diff)
Merge branch 'net-stmmac-increase-clk_ptp_ref-rate'
Andrew Halaney says: ==================== net: stmmac: Increase clk_ptp_ref rate This series aims to increase the clk_ptp_ref rate to get the best possible PTP timestamping resolution possible. Some modified disclosure about my development/testing process from the RFC/RFT v1 follows. Disclosure: I don't know much about PTP beyond what you can google in an afternoon, don't have access to documentation about the stmmac IP, and have only tested that (based on code comments and git commit history) the programming of the subsecond register (and the clock rate) makes more sense with these changes. Qualcomm has tested a similar change offlist, verifying PTP more formally as I understand it. The last version was an RFC/RFT, but I didn't get a lot of confirmation that doing patch 3 in that series (essentially setting clk_ptp_ref to whatever its max value is) for the whole stmmac ecosystem was a safe idea. So I am erring on the side of caution and doing this for the Qualcomm platform only. See v1 for an approach that would apply to all stmmac platform drivers with clk_ptp_ref. v1: https://lore.kernel.org/netdev/20230711205732.364954-1-ahalaney@redhat.com/ ==================== Link: https://lore.kernel.org/r/20230725211853.895832-2-ahalaney@redhat.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c3
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c18
2 files changed, 19 insertions, 2 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
index 0ffae785d8bd..979c755964b1 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
@@ -257,9 +257,8 @@ static void intel_speed_mode_2500(struct net_device *ndev, void *intel_data)
/* Program PTP Clock Frequency for different variant of
* Intel mGBE that has slightly different GPO mapping
*/
-static void intel_mgbe_ptp_clk_freq_config(void *npriv)
+static void intel_mgbe_ptp_clk_freq_config(struct stmmac_priv *priv)
{
- struct stmmac_priv *priv = (struct stmmac_priv *)npriv;
struct intel_priv_data *intel_priv;
u32 gpio_value;
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index 735525ba8b93..a85501874801 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -694,6 +694,23 @@ static void ethqos_clks_disable(void *data)
ethqos_clks_config(data, false);
}
+static void ethqos_ptp_clk_freq_config(struct stmmac_priv *priv)
+{
+ struct plat_stmmacenet_data *plat_dat = priv->plat;
+ int err;
+
+ if (!plat_dat->clk_ptp_ref)
+ return;
+
+ /* Max the PTP ref clock out to get the best resolution possible */
+ err = clk_set_rate(plat_dat->clk_ptp_ref, ULONG_MAX);
+ if (err)
+ netdev_err(priv->dev, "Failed to max out clk_ptp_ref: %d\n", err);
+ plat_dat->clk_ptp_rate = clk_get_rate(plat_dat->clk_ptp_ref);
+
+ netdev_dbg(priv->dev, "PTP rate %d\n", plat_dat->clk_ptp_rate);
+}
+
static int qcom_ethqos_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
@@ -779,6 +796,7 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
plat_dat->bsp_priv = ethqos;
plat_dat->fix_mac_speed = ethqos_fix_mac_speed;
plat_dat->dump_debug_regs = rgmii_dump;
+ plat_dat->ptp_clk_freq_config = ethqos_ptp_clk_freq_config;
plat_dat->has_gmac4 = 1;
if (ethqos->has_emac_ge_3)
plat_dat->dwmac4_addrs = &data->dwmac4_addrs;