diff options
| author | Dave Jiang <dave.jiang@intel.com> | 2020-11-23 08:36:12 -0700 |
|---|---|---|
| committer | Jon Mason <jdmason@kudzu.us> | 2020-12-06 18:18:03 -0500 |
| commit | 75b6f6487cedd0e4c8e07d68b68b8f85cd352bfe (patch) | |
| tree | 36832eee46f53a6995e5af0b614047f71af9af86 /drivers/ntb/hw/intel/ntb_hw_gen4.c | |
| parent | 91b8246de8590bac89b03b4fd14c61a8b4053b9e (diff) | |
ntb: intel: add Intel NTB LTR vendor support for gen4 NTB
Intel NTB device has custom LTR management that is not compliant with the
PCIe standard. Add support to set LTR status triggered by link status
change.
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jon Mason <jdmason@kudzu.us>
Diffstat (limited to 'drivers/ntb/hw/intel/ntb_hw_gen4.c')
| -rw-r--r-- | drivers/ntb/hw/intel/ntb_hw_gen4.c | 27 |
1 files changed, 26 insertions, 1 deletions
diff --git a/drivers/ntb/hw/intel/ntb_hw_gen4.c b/drivers/ntb/hw/intel/ntb_hw_gen4.c index bc4541cbf8c6..fede05151f69 100644 --- a/drivers/ntb/hw/intel/ntb_hw_gen4.c +++ b/drivers/ntb/hw/intel/ntb_hw_gen4.c @@ -177,8 +177,10 @@ int gen4_init_dev(struct intel_ntb_dev *ndev) ndev->reg = &gen4_reg; - if (pdev_is_ICX(pdev)) + if (pdev_is_ICX(pdev)) { ndev->hwerr_flags |= NTB_HWERR_BAR_ALIGN; + ndev->hwerr_flags |= NTB_HWERR_LTR_BAD; + } ppd1 = ioread32(ndev->self_mmio + GEN4_PPD1_OFFSET); ndev->ntb.topo = gen4_ppd_topo(ndev, ppd1); @@ -431,6 +433,25 @@ static int intel_ntb4_link_enable(struct ntb_dev *ntb, dev_dbg(&ntb->pdev->dev, "ignoring max_width %d\n", max_width); + if (!(ndev->hwerr_flags & NTB_HWERR_LTR_BAD)) { + u32 ltr; + + /* Setup active snoop LTR values */ + ltr = NTB_LTR_ACTIVE_REQMNT | NTB_LTR_ACTIVE_VAL | NTB_LTR_ACTIVE_LATSCALE; + /* Setup active non-snoop values */ + ltr = (ltr << NTB_LTR_NS_SHIFT) | ltr; + iowrite32(ltr, ndev->self_mmio + GEN4_LTR_ACTIVE_OFFSET); + + /* Setup idle snoop LTR values */ + ltr = NTB_LTR_IDLE_VAL | NTB_LTR_IDLE_LATSCALE | NTB_LTR_IDLE_REQMNT; + /* Setup idle non-snoop values */ + ltr = (ltr << NTB_LTR_NS_SHIFT) | ltr; + iowrite32(ltr, ndev->self_mmio + GEN4_LTR_IDLE_OFFSET); + + /* setup PCIe LTR to active */ + iowrite8(NTB_LTR_SWSEL_ACTIVE, ndev->self_mmio + GEN4_LTR_SWSEL_OFFSET); + } + ntb_ctl = NTB_CTL_E2I_BAR23_SNOOP | NTB_CTL_I2E_BAR23_SNOOP; ntb_ctl |= NTB_CTL_E2I_BAR45_SNOOP | NTB_CTL_I2E_BAR45_SNOOP; iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl); @@ -476,6 +497,10 @@ static int intel_ntb4_link_disable(struct ntb_dev *ntb) lnkctl |= GEN4_LINK_CTRL_LINK_DISABLE; iowrite16(lnkctl, ndev->self_mmio + GEN4_LINK_CTRL_OFFSET); + /* set LTR to idle */ + if (!(ndev->hwerr_flags & NTB_HWERR_LTR_BAD)) + iowrite8(NTB_LTR_SWSEL_IDLE, ndev->self_mmio + GEN4_LTR_SWSEL_OFFSET); + ndev->dev_up = 0; return 0; |