diff options
| author | Dave Jiang <dave.jiang@intel.com> | 2020-06-05 08:13:34 -0700 |
|---|---|---|
| committer | Jon Mason <jdmason@kudzu.us> | 2020-06-05 20:02:00 -0400 |
| commit | 134a86545c6072c049a2c6e77d6843e650df511d (patch) | |
| tree | cbe362acb35c0da640f731df53880cba7162a22a /drivers/ntb/hw/intel/ntb_hw_gen4.h | |
| parent | 26bfe3d0b227ab6d38692640b44ce48f2d857602 (diff) | |
ntb: intel: add hw workaround for NTB BAR alignment
Add NTB_HWERR_BAR_ALIGN hw errata flag to work around issue where the
aligment for the XLAT base must be BAR size aligned rather than 4k page
aligned. On ICX platform, the XLAT base can be 4k page size aligned
rather than BAR size aligned unlike the previous gen Intel NTB. However,
a silicon errata prevented this from working as expected and a workaround
is introduced to resolve the issue.
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jon Mason <jdmason@kudzu.us>
Diffstat (limited to 'drivers/ntb/hw/intel/ntb_hw_gen4.h')
| -rw-r--r-- | drivers/ntb/hw/intel/ntb_hw_gen4.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/ntb/hw/intel/ntb_hw_gen4.h b/drivers/ntb/hw/intel/ntb_hw_gen4.h index 7d7a82e8518d..a868c788de02 100644 --- a/drivers/ntb/hw/intel/ntb_hw_gen4.h +++ b/drivers/ntb/hw/intel/ntb_hw_gen4.h @@ -5,6 +5,10 @@ #include "ntb_hw_intel.h" +/* Supported PCI device revision range for ICX */ +#define PCI_DEVICE_REVISION_ICX_MIN 0x2 +#define PCI_DEVICE_REVISION_ICX_MAX 0xF + /* Intel Gen4 NTB hardware */ /* PCIe config space */ #define GEN4_IMBAR23SZ_OFFSET 0x00c4 @@ -84,4 +88,13 @@ ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf, extern const struct ntb_dev_ops intel_ntb4_ops; +static inline int pdev_is_ICX(struct pci_dev *pdev) +{ + if (pdev_is_gen4(pdev) && + pdev->revision >= PCI_DEVICE_REVISION_ICX_MIN && + pdev->revision <= PCI_DEVICE_REVISION_ICX_MAX) + return 1; + return 0; +} + #endif |