diff options
| author | Jon Mason <jon.mason@intel.com> | 2013-07-15 16:43:54 -0700 |
|---|---|---|
| committer | Jon Mason <jon.mason@intel.com> | 2013-09-05 11:07:58 -0700 |
| commit | ed6c24eda97b6bdcd013dbd91cc5c8b02de507e9 (patch) | |
| tree | 992940462fcdf730a3c93af95dd051b8a543f6ff /drivers/ntb/ntb_regs.h | |
| parent | 497938890a0121d040683aa1db42cad8daf7ae97 (diff) | |
NTB: NTB-RP support
Add support for Non-Transparent Bridge connected to a PCI-E Root Port on
the remote system (also known as NTB-RP mode). This allows for a NTB
enabled system to be connected to a non-NTB enabled system/slot.
Modifications to the registers and BARs/MWs on the Secondary side by the
remote system are reflected into registers on the Primary side for the
local system. Similarly, modifications of registers and BARs/MWs on
Primary side by the local system are reflected into registers on the
Secondary side for the Remote System. This allows communication between
the 2 sides via these registers and BARs/MWs.
Note: there is not a fix for the Xeon Errata (that was already worked
around in NTB-B2B mode) for NTB-RP mode. Due to this limitation, NTB-RP
will not work on the Secondary side with the Xeon Errata workaround
enabled. To get around this, disable the workaround via the
xeon_errata_workaround=0 modparm. However, this can cause the hang
described in the errata.
Signed-off-by: Jon Mason <jon.mason@intel.com>
Diffstat (limited to 'drivers/ntb/ntb_regs.h')
| -rw-r--r-- | drivers/ntb/ntb_regs.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/ntb/ntb_regs.h b/drivers/ntb/ntb_regs.h index 03a66ef32a68..b4f4604f4ce5 100644 --- a/drivers/ntb/ntb_regs.h +++ b/drivers/ntb/ntb_regs.h @@ -46,8 +46,6 @@ * Jon Mason <jon.mason@intel.com> */ -#define NTB_LINK_ENABLE 0x0000 -#define NTB_LINK_DISABLE 0x0002 #define NTB_LINK_STATUS_ACTIVE 0x2000 #define NTB_LINK_SPEED_MASK 0x000f #define NTB_LINK_WIDTH_MASK 0x03f0 @@ -65,6 +63,7 @@ #define SNB_PCICMD_OFFSET 0x0504 #define SNB_DEVCTRL_OFFSET 0x0598 +#define SNB_SLINK_STATUS_OFFSET 0x05A2 #define SNB_LINK_STATUS_OFFSET 0x01A2 #define SNB_PBAR2LMT_OFFSET 0x0000 @@ -147,6 +146,8 @@ #define BWD_LTSSMSTATEJMP_FORCEDETECT (1 << 2) #define BWD_IBIST_ERR_OFLOW 0x7FFF7FFF +#define NTB_CNTL_CFG_LOCK (1 << 0) +#define NTB_CNTL_LINK_DISABLE (1 << 1) #define NTB_CNTL_BAR23_SNOOP (1 << 2) #define NTB_CNTL_BAR45_SNOOP (1 << 6) #define BWD_CNTL_LINK_DOWN (1 << 16) |