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authorSrikanth Thokala <srikanth.thokala@intel.com>2021-08-06 02:40:10 +0530
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2021-08-20 13:47:05 +0100
commit0c87f90b4c13586a00fbe63524c7be197609d8dc (patch)
tree71f7482c3bef2828edbcdbe7b0870856d27977b3 /drivers/pci/controller/dwc/Makefile
parent33d2f8e4ffd144a0b0c9968558820af0164a2d53 (diff)
PCI: keembay: Add support for Intel Keem Bay
Add driver for Intel Keem Bay SoC PCIe controller. This controller is based on DesignWare PCIe core. In Root Complex mode, only internal reference clock is possible for Keem Bay A0. For Keem Bay B0, external reference clock can be used and will be the default configuration. Currently, keembay_pcie_of_data structure has one member. It will be expanded later to handle this difference. Endpoint mode link initialization is handled by the boot firmware. Link: https://lore.kernel.org/r/20210805211010.29484-3-srikanth.thokala@intel.com Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Signed-off-by: Srikanth Thokala <srikanth.thokala@intel.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Krzysztof WilczyƄski <kw@linux.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Diffstat (limited to 'drivers/pci/controller/dwc/Makefile')
-rw-r--r--drivers/pci/controller/dwc/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index 9e6ce0dc2f53..8b3e7176b4bf 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o
+obj-$(CONFIG_PCIE_KEEMBAY) += pcie-keembay.o
obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
obj-$(CONFIG_PCI_MESON) += pci-meson.o