diff options
| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2022-09-14 13:23:44 +0530 |
|---|---|---|
| committer | Lorenzo Pieralisi <lpieralisi@kernel.org> | 2022-10-05 16:17:45 +0200 |
| commit | c457ac029e443faa5886f59f849e94701375b80f (patch) | |
| tree | 8357ffc45cb1c254945259e464b797a89fe3ddba /drivers/pci/controller/dwc/pcie-qcom-ep.c | |
| parent | 6dbba2b53c3bcbbee849d2fa8cf6acc973ab2e81 (diff) | |
PCI: qcom-ep: Gate Master AXI clock to MHI bus during L1SS
During L1SS, gate the Master clock supplied to the MHI bus to save power.
Link: https://lore.kernel.org/r/20220914075350.7992-7-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-qcom-ep.c')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-qcom-ep.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index d4f2437ba735..5502e627e482 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -27,6 +27,7 @@ #define PARF_SYS_CTRL 0x00 #define PARF_DB_CTRL 0x10 #define PARF_PM_CTRL 0x20 +#define PARF_MHI_CLOCK_RESET_CTRL 0x174 #define PARF_MHI_BASE_ADDR_LOWER 0x178 #define PARF_MHI_BASE_ADDR_UPPER 0x17c #define PARF_DEBUG_INT_EN 0x190 @@ -89,6 +90,9 @@ #define PARF_PM_CTRL_READY_ENTR_L23 BIT(2) #define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5) +/* PARF_MHI_CLOCK_RESET_CTRL fields */ +#define PARF_MSTR_AXI_CLK_EN BIT(1) + /* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */ #define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN BIT(0) @@ -394,6 +398,11 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER); writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER); + /* Gate Master AXI clock to MHI bus during L1SS */ + val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL); + val &= ~PARF_MSTR_AXI_CLK_EN; + val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL); + dw_pcie_ep_init_notify(&pcie_ep->pci.ep); /* Enable LTSSM */ |