diff options
| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2023-10-04 22:14:29 +0530 |
|---|---|---|
| committer | Krzysztof Wilczyński <kwilczynski@kernel.org> | 2023-10-14 19:18:36 +0000 |
| commit | dc2f2a9d1cf2c505efbb8b7e782a7f22e635f4bf (patch) | |
| tree | 5176b60995db551f1297c022950ce99133834b57 /drivers/pci/controller/dwc/pcie-qcom-ep.c | |
| parent | 8da2e9af0bb5217361f4ddde0d9b820b45c185e8 (diff) | |
PCI: qcom-ep: Use PCIE_SPEED2MBS_ENC() macro for encoding link speed
Instead of hardcoding the link speed in MBps, use existing
PCIE_SPEED2MBS_ENC() macro that does the encoding of the link speed for
us. Also, let's Wrap it with QCOM_PCIE_LINK_SPEED_TO_BW() macro to do
the conversion to ICC speed.
This eliminates the need for a switch case in qcom_pcie_icc_update() and
also works for future Gen speeds without any code modifications.
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/linux-pci/20231004164430.39662-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-qcom-ep.c')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-qcom-ep.c | 31 |
1 files changed, 6 insertions, 25 deletions
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 8bd8107690a6..32c8d9e37876 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -23,6 +23,7 @@ #include <linux/reset.h> #include <linux/module.h> +#include "../../pci.h" #include "pcie-designware.h" /* PARF registers */ @@ -135,10 +136,8 @@ #define CORE_RESET_TIME_US_MAX 1005 #define WAKE_DELAY_US 2000 /* 2 ms */ -#define PCIE_GEN1_BW_MBPS 250 -#define PCIE_GEN2_BW_MBPS 500 -#define PCIE_GEN3_BW_MBPS 985 -#define PCIE_GEN4_BW_MBPS 1969 +#define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \ + Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed])) #define to_pcie_ep(x) dev_get_drvdata((x)->dev) @@ -266,7 +265,7 @@ static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) { struct dw_pcie *pci = &pcie_ep->pci; - u32 offset, status, bw; + u32 offset, status; int speed, width; int ret; @@ -279,25 +278,7 @@ static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); - switch (speed) { - case 1: - bw = MBps_to_icc(PCIE_GEN1_BW_MBPS); - break; - case 2: - bw = MBps_to_icc(PCIE_GEN2_BW_MBPS); - break; - case 3: - bw = MBps_to_icc(PCIE_GEN3_BW_MBPS); - break; - default: - dev_warn(pci->dev, "using default GEN4 bandwidth\n"); - fallthrough; - case 4: - bw = MBps_to_icc(PCIE_GEN4_BW_MBPS); - break; - } - - ret = icc_set_bw(pcie_ep->icc_mem, 0, width * bw); + ret = icc_set_bw(pcie_ep->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); if (ret) dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", ret); @@ -335,7 +316,7 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) * Set an initial peak bandwidth corresponding to single-lane Gen 1 * for the pcie-mem path. */ - ret = icc_set_bw(pcie_ep->icc_mem, 0, MBps_to_icc(PCIE_GEN1_BW_MBPS)); + ret = icc_set_bw(pcie_ep->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); if (ret) { dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", ret); |