diff options
| author | Thippeswamy Havalige <thippeswamy.havalige@amd.com> | 2023-10-03 23:04:53 +0530 |
|---|---|---|
| committer | Krzysztof Wilczyński <kwilczynski@kernel.org> | 2023-10-26 15:02:02 +0000 |
| commit | 8d786149d78c7784144c7179e25134b6530b714b (patch) | |
| tree | 6029c56291d0a559673c3a51222fa3308ab7d4ee /drivers/pci/controller/pcie-xilinx-common.h | |
| parent | 4ae1cd7d4be2d1388bcfcd8371eb001a4cec88e2 (diff) | |
PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver
Add support for Xilinx XDMA Soft IP core as Root Port.
The Zynq UltraScale+ MPSoCs devices support XDMA soft IP module in
programmable logic.
The integrated XDMA Soft IP block has integrated bridge function that
can act as PCIe Root Port.
[kwilczynski: correct indentation and whitespaces, Kconfig help update]
Link: https://lore.kernel.org/linux-pci/20231003173453.938190-4-thippeswamy.havalige@amd.com
Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Diffstat (limited to 'drivers/pci/controller/pcie-xilinx-common.h')
| -rw-r--r-- | drivers/pci/controller/pcie-xilinx-common.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/pci/controller/pcie-xilinx-common.h b/drivers/pci/controller/pcie-xilinx-common.h index e97d27252a08..1832770f3308 100644 --- a/drivers/pci/controller/pcie-xilinx-common.h +++ b/drivers/pci/controller/pcie-xilinx-common.h @@ -19,6 +19,7 @@ #define XILINX_PCIE_INTR_PME_TO_ACK_RCVD 15 #define XILINX_PCIE_INTR_INTX 16 #define XILINX_PCIE_INTR_PM_PME_RCVD 17 +#define XILINX_PCIE_INTR_MSI 17 #define XILINX_PCIE_INTR_SLV_UNSUPP 20 #define XILINX_PCIE_INTR_SLV_UNEXP 21 #define XILINX_PCIE_INTR_SLV_COMPL 22 |