diff options
| author | Thippeswamy Havalige <thippeswamy.havalige@amd.com> | 2023-10-03 23:04:51 +0530 |
|---|---|---|
| committer | Krzysztof Wilczyński <kwilczynski@kernel.org> | 2023-10-26 14:10:42 +0000 |
| commit | a977ee945e9490fabd33dcc33399e992252598cf (patch) | |
| tree | 392511b9298dad194cd099a2a81a77d5a86bd4c7 /drivers/pci/controller/pcie-xilinx-common.h | |
| parent | 0bb80ecc33a8fb5a682236443c1e740d5c917d1d (diff) | |
PCI: xilinx-cpm: Move IRQ definitions to a common header
Move the interrupt bit definitions to the pcie-xilinx-common.h file,
which then can be shared between pcie-xilinx-cpm and the new xilinx-xdma
drivers.
While at it, also rename them so these definitions are not CPM-specific.
No functional change intended.
[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20231003173453.938190-2-thippeswamy.havalige@amd.com
Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Diffstat (limited to 'drivers/pci/controller/pcie-xilinx-common.h')
| -rw-r--r-- | drivers/pci/controller/pcie-xilinx-common.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/pci/controller/pcie-xilinx-common.h b/drivers/pci/controller/pcie-xilinx-common.h new file mode 100644 index 000000000000..e97d27252a08 --- /dev/null +++ b/drivers/pci/controller/pcie-xilinx-common.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2023, Xilinx, Inc. + */ + +#include <linux/pci.h> +#include <linux/pci-ecam.h> +#include <linux/platform_device.h> + +/* Interrupt registers definitions */ +#define XILINX_PCIE_INTR_LINK_DOWN 0 +#define XILINX_PCIE_INTR_HOT_RESET 3 +#define XILINX_PCIE_INTR_CFG_PCIE_TIMEOUT 4 +#define XILINX_PCIE_INTR_CFG_TIMEOUT 8 +#define XILINX_PCIE_INTR_CORRECTABLE 9 +#define XILINX_PCIE_INTR_NONFATAL 10 +#define XILINX_PCIE_INTR_FATAL 11 +#define XILINX_PCIE_INTR_CFG_ERR_POISON 12 +#define XILINX_PCIE_INTR_PME_TO_ACK_RCVD 15 +#define XILINX_PCIE_INTR_INTX 16 +#define XILINX_PCIE_INTR_PM_PME_RCVD 17 +#define XILINX_PCIE_INTR_SLV_UNSUPP 20 +#define XILINX_PCIE_INTR_SLV_UNEXP 21 +#define XILINX_PCIE_INTR_SLV_COMPL 22 +#define XILINX_PCIE_INTR_SLV_ERRP 23 +#define XILINX_PCIE_INTR_SLV_CMPABT 24 +#define XILINX_PCIE_INTR_SLV_ILLBUR 25 +#define XILINX_PCIE_INTR_MST_DECERR 26 +#define XILINX_PCIE_INTR_MST_SLVERR 27 +#define XILINX_PCIE_INTR_SLV_PCIE_TIMEOUT 28 |