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| author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2021-07-18 18:56:58 -0700 |
|---|---|---|
| committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2021-07-18 18:56:58 -0700 |
| commit | 320424c7d44f54c18df9812fd7c45f6963524002 (patch) | |
| tree | 5853aff866a321d476f5e4f2a3de5b5e90408580 /drivers/pci/controller/pcie-xilinx-nwl.c | |
| parent | f8f84af5da9ee04ef1d271528656dac42a090d00 (diff) | |
| parent | 62fb9874f5da54fdb243003b386128037319b219 (diff) | |
Merge tag 'v5.13' into next
Sync up with the mainline to get the latest parport API.
Diffstat (limited to 'drivers/pci/controller/pcie-xilinx-nwl.c')
| -rw-r--r-- | drivers/pci/controller/pcie-xilinx-nwl.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 07e36661bbc2..8689311c5ef6 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -26,6 +26,7 @@ /* Bridge core config registers */ #define BRCFG_PCIE_RX0 0x00000000 +#define BRCFG_PCIE_RX1 0x00000004 #define BRCFG_INTERRUPT 0x00000010 #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020 @@ -128,6 +129,7 @@ #define NWL_ECAM_VALUE_DEFAULT 12 #define CFG_DMA_REG_BAR GENMASK(2, 0) +#define CFG_PCIE_CACHE GENMASK(7, 0) #define INT_PCI_MSI_NR (2 * 32) @@ -675,6 +677,11 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK, BRCFG_PCIE_RX_MSG_FILTER); + /* This routes the PCIe DMA traffic to go through CCI path */ + if (of_dma_is_coherent(dev->of_node)) + nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) | + CFG_PCIE_CACHE, BRCFG_PCIE_RX1); + err = nwl_wait_for_link(pcie); if (err) return err; |