diff options
| author | Bjorn Helgaas <bhelgaas@google.com> | 2016-10-06 13:25:46 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2016-10-11 08:30:33 -0500 |
| commit | ad8802189426cf7b3a2ad0444f71981fb81312a8 (patch) | |
| tree | 524f4559a9f5c984a31bb977f5ab9e384586d57c /drivers/pci/host/pci-exynos.c | |
| parent | 7e00dfd0fbbb2fc276592613f76ded0b9a139a04 (diff) | |
PCI: designware: Swap order of dw_pcie_writel_rc() reg/val arguments
Swap order of dw_pcie_writel_rc() arguments to match the "dev, pos, val"
order used by pci_write_config_word() and other drivers. No functional
change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/host/pci-exynos.c')
| -rw-r--r-- | drivers/pci/host/pci-exynos.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c index b29e9d64d41b..f559b494f300 100644 --- a/drivers/pci/host/pci-exynos.c +++ b/drivers/pci/host/pci-exynos.c @@ -435,7 +435,7 @@ static inline u32 exynos_pcie_readl_rc(struct pcie_port *pp, u32 reg) return val; } -static inline void exynos_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg) +static inline void exynos_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val) { exynos_pcie_sideband_dbi_w_mode(pp, true); writel(val, pp->dbi_base + reg); |