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authorBharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>2016-09-01 15:44:42 +0530
committerBjorn Helgaas <bhelgaas@google.com>2016-09-13 10:38:19 -0500
commit3cd049ab9edd48a41955b8d05f0bc57ead918456 (patch)
tree8c02857a2f569c5a83e97f5626242b8185d97178 /drivers/pci/host/pcie-xilinx.c
parentb584fa1fde71aa57fb63d32f66ff6c192ff7f2c5 (diff)
PCI: xilinx: Clear interrupt register for invalid interrupt
The interrupt decode register is not being cleared if an invalid interrupt arises. Clear the decode register in this case. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/pci/host/pcie-xilinx.c')
-rw-r--r--drivers/pci/host/pcie-xilinx.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index bd646772b001..de1c758d17d7 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -434,7 +434,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
/* Check whether interrupt valid */
if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
dev_warn(port->dev, "RP Intr FIFO1 read error\n");
- return IRQ_HANDLED;
+ goto error;
}
if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) {
@@ -456,7 +456,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
dev_warn(port->dev, "RP Intr FIFO1 read error\n");
- return IRQ_HANDLED;
+ goto error;
}
if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {
@@ -501,6 +501,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
if (status & XILINX_PCIE_INTR_MST_ERRP)
dev_warn(port->dev, "Master error poison\n");
+error:
/* Clear the Interrupt Decode register */
pcie_write(port, status, XILINX_PCIE_REG_IDR);