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authorBjorn Helgaas <bhelgaas@google.com>2020-09-29 14:24:11 -0500
committerBjorn Helgaas <bhelgaas@google.com>2020-09-30 17:01:46 -0500
commit638c133e5f52a3793cb5494897df008f5cef0ddd (patch)
treee6096ced43b63c67477a8a04e199150990deed8d /drivers/pci/pci.h
parent454d082dbb47febbfe2998c3953e62cd917abbbf (diff)
PCI/PM: Revert "PCI/PM: Apply D2 delay as milliseconds, not microseconds"
This reverts commit 7e24bc347e57992d532bc2ed700209b0fc0a4bf5. 7e24bc347e57 was based on PCIe r5.0, sec 5.9, which claims we need a 200 ms delay when transitioning to or from D2. However, sec 5.3.1.3 states the delay as 200 μs (microseconds), as does the table in PCIe r4.0, sec 5.9.1. This looks like a typo in the r5.0 spec, so revert back to a 200 μs delay instead of a 200 ms delay. Fixes: 7e24bc347e57 ("PCI/PM: Apply D2 delay as milliseconds, not microseconds") Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'drivers/pci/pci.h')
-rw-r--r--drivers/pci/pci.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index f0a9cbe01bc7..f86cae9aa1f4 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -43,9 +43,9 @@ int pci_probe_reset_function(struct pci_dev *dev);
int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
int pci_bus_error_reset(struct pci_dev *dev);
-#define PCI_PM_D2_DELAY 200
-#define PCI_PM_D3HOT_WAIT 10
-#define PCI_PM_D3COLD_WAIT 100
+#define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
+#define PCI_PM_D3HOT_WAIT 10 /* msec */
+#define PCI_PM_D3COLD_WAIT 100 /* msec */
/**
* struct pci_platform_pm_ops - Firmware PM callbacks