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authorBjorn Helgaas <bhelgaas@google.com>2023-06-26 12:59:57 -0500
committerBjorn Helgaas <bhelgaas@google.com>2023-06-26 12:59:57 -0500
commit283810ac54a2b8a179fd4f30fd9f05907b397fcd (patch)
tree2f4ea2abdb77d53ecc665fa5ad2a81f8ac92afa8 /drivers/pci/quirks.c
parentd0b7b3a422f1f550a1bac9fc3404196c10232d14 (diff)
parent88d341716b83abd355558523186ca488918627ee (diff)
Merge branch 'pci/virtualization'
- Delay extra 250ms after FLR of Solidigm P44 Pro NVMe to avoid KVM hang when guest is rebooted (Mike Pastore) - Add function 1 DMA alias quirk for Marvell 88SE9235 (Robin Murphy) * pci/virtualization: PCI: Add function 1 DMA alias quirk for Marvell 88SE9235 PCI: Delay after FLR of Solidigm P44 Pro NVMe
Diffstat (limited to 'drivers/pci/quirks.c')
-rw-r--r--drivers/pci/quirks.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 1c4f715537c1..f83cc7805297 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -4086,10 +4086,11 @@ static int nvme_disable_and_flr(struct pci_dev *dev, bool probe)
}
/*
- * Intel DC P3700 NVMe controller will timeout waiting for ready status
- * to change after NVMe enable if the driver starts interacting with the
- * device too soon after FLR. A 250ms delay after FLR has heuristically
- * proven to produce reliably working results for device assignment cases.
+ * Some NVMe controllers such as Intel DC P3700 and Solidigm P44 Pro will
+ * timeout waiting for ready status to change after NVMe enable if the driver
+ * starts interacting with the device too soon after FLR. A 250ms delay after
+ * FLR has heuristically proven to produce reliably working results for device
+ * assignment cases.
*/
static int delay_250ms_after_flr(struct pci_dev *dev, bool probe)
{
@@ -4176,6 +4177,7 @@ static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
{ PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
{ PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
{ PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr },
+ { PCI_VENDOR_ID_SOLIDIGM, 0xf1ac, delay_250ms_after_flr },
{ PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
reset_chelsio_generic_dev },
{ PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF,
@@ -4267,6 +4269,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
quirk_dma_func1_alias);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235,
+ quirk_dma_func1_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
quirk_dma_func1_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,