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authorBjorn Helgaas <bhelgaas@google.com>2024-01-15 12:10:36 -0600
committerBjorn Helgaas <bhelgaas@google.com>2024-01-15 12:10:36 -0600
commitc94df6214681da71c32268771fa89540de423567 (patch)
tree1de4bb3ad59206ba21f6504d0ec7461c3e80abd3 /drivers/pci
parentd6f5bcc2d098b5900fc288429499d6a7e650717f (diff)
parente367e3c765f5477b2e79da0f1399aed49e2d1e37 (diff)
Merge branch 'pci/virtualization'
- Add ACS quirk for more Zhaoxin Root Ports (LeoLiuoc) * pci/virtualization: PCI: Add ACS quirk for more Zhaoxin Root Ports
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/quirks.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 248d051ec7fa..e4bf0ed46393 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -4709,17 +4709,21 @@ static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
* But the implementation could block peer-to-peer transactions between them
* and provide ACS-like functionality.
*/
-static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags)
+static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags)
{
if (!pci_is_pcie(dev) ||
((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
(pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
return -ENOTTY;
+ /*
+ * Future Zhaoxin Root Ports and Switch Downstream Ports will
+ * implement ACS capability in accordance with the PCIe Spec.
+ */
switch (dev->device) {
case 0x0710 ... 0x071e:
case 0x0721:
- case 0x0723 ... 0x0732:
+ case 0x0723 ... 0x0752:
return pci_acs_ctrl_enabled(acs_flags,
PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
}