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authorHonghui Zhang <honghui.zhang@mediatek.com>2019-02-01 13:36:07 +0800
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2019-03-01 11:22:21 +0000
commitcbe3a7728c7ad4721677208e155db06f67eb57d2 (patch)
tree919e48c3264e73bfbb411f0cc2e38018586a6417 /drivers/pci
parentc61df57343bf05743f8abbb31eec9a6f05820dd1 (diff)
PCI: mediatek: Enlarge PCIe2AHB window size to support 4GB DRAM
The PCIE_AXI_WINDOW0 register defines the inbound window size for requests coming from PCI endpoints. Requests outside of this window will be treated as unsupported requests. Enlarge this window size from 2^31 to 2^33 to support a 8GB address space (which gives endpoints DMA access to full 4GB DRAM address range - physical DRAM starts at 0x40000000). Reported-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/controller/pcie-mediatek.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index c42fe5c4319f..0b6c72804e03 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -90,6 +90,12 @@
#define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
#define PCIE_AXI_WINDOW0 0x448
#define WIN_ENABLE BIT(7)
+/*
+ * Define PCIe to AHB window size as 2^33 to support max 8GB address space
+ * translate, support least 4GB DRAM size access from EP DMA(physical DRAM
+ * start from 0x40000000).
+ */
+#define PCIE2AHB_SIZE 0x21
/* PCIe V2 configuration transaction header */
#define PCIE_CFG_HEADER0 0x460
@@ -713,7 +719,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
/* Set PCIe to AXI translation memory space.*/
- val = fls(0xffffffff) | WIN_ENABLE;
+ val = PCIE2AHB_SIZE | WIN_ENABLE;
writel(val, port->base + PCIE_AXI_WINDOW0);
return 0;