diff options
| author | Shawn Lin <shawn.lin@rock-chips.com> | 2017-05-04 10:24:51 +0800 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2017-07-02 18:45:56 -0500 |
| commit | 09cac05097535015f0a0d64c051f17fd8c65c6bb (patch) | |
| tree | 2c465ba13f9d16494c68cbeee03fa9f9a53a7a58 /drivers/pci | |
| parent | 5667e655e1c77e0dec3f146a0d2484818583a800 (diff) | |
PCI: rockchip: Reconfigure configuration space header type
Per PCIe base specification (Revision 3.1a), section 7.5.3, type 1
configuration space header should be used when accessing PCIe switch. So
we need to reconfigure the header according to the bus number we are
accessing. Otherwise we could not visit the buses behind the switch.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/host/pcie-rockchip.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index 1b9c58dc7d4c..c283633181d3 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -378,6 +378,13 @@ static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip, return PCIBIOS_BAD_REGISTER_NUMBER; } + if (bus->parent->number == rockchip->root_bus_nr) + rockchip_pcie_cfg_configuration_accesses(rockchip, + AXI_WRAPPER_TYPE0_CFG); + else + rockchip_pcie_cfg_configuration_accesses(rockchip, + AXI_WRAPPER_TYPE1_CFG); + if (size == 4) { *val = readl(rockchip->reg_base + busdev); } else if (size == 2) { @@ -402,6 +409,13 @@ static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip, if (!IS_ALIGNED(busdev, size)) return PCIBIOS_BAD_REGISTER_NUMBER; + if (bus->parent->number == rockchip->root_bus_nr) + rockchip_pcie_cfg_configuration_accesses(rockchip, + AXI_WRAPPER_TYPE0_CFG); + else + rockchip_pcie_cfg_configuration_accesses(rockchip, + AXI_WRAPPER_TYPE1_CFG); + if (size == 4) writel(val, rockchip->reg_base + busdev); else if (size == 2) |