diff options
| author | Ingo Molnar <mingo@kernel.org> | 2020-03-21 09:35:44 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2020-03-21 09:35:44 +0100 |
| commit | df10846ff2ac3b0a7b295be2de2e9215877982f3 (patch) | |
| tree | 9e5ff5583aa1547afd3c577815af81c2f328e288 /drivers/perf/fsl_imx8_ddr_perf.c | |
| parent | a4654e9bde4ecedb4921e6c8fe2088114bdff1b3 (diff) | |
| parent | 5ad0ec0b86525d0c5d3d250d3cfad7f183b00cfa (diff) | |
Merge branch 'linus' into locking/kcsan, to pick up fixes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'drivers/perf/fsl_imx8_ddr_perf.c')
| -rw-r--r-- | drivers/perf/fsl_imx8_ddr_perf.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index 95dca2cb5265..90884d14f95f 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -388,9 +388,10 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, if (enable) { /* - * must disable first, then enable again - * otherwise, cycle counter will not work - * if previous state is enabled. + * cycle counter is special which should firstly write 0 then + * write 1 into CLEAR bit to clear it. Other counters only + * need write 0 into CLEAR bit and it turns out to be 1 by + * hardware. Below enable flow is harmless for all counters. */ writel(0, pmu->base + reg); val = CNTL_EN | CNTL_CLEAR; @@ -398,7 +399,8 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, writel(val, pmu->base + reg); } else { /* Disable counter */ - writel(0, pmu->base + reg); + val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK; + writel(val, pmu->base + reg); } } |