diff options
| author | Maxime Ripard <maxime@cerno.tech> | 2021-10-25 17:29:03 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime@cerno.tech> | 2021-11-04 10:37:14 +0100 |
| commit | 16e101051f329f5f3f2dd810f3687d166580aa3a (patch) | |
| tree | 5afe5be64e8f06650a940cee93b050d6b4b59a56 /drivers/phy/intel/phy-intel-keembay-usb.c | |
| parent | b7551457c5d0b3505b0be247d47919c1ee30506d (diff) | |
drm/vc4: Increase the core clock based on HVS load
Depending on a given HVS output (HVS to PixelValves) and input (planes
attached to a channel) load, the HVS needs for the core clock to be
raised above its boot time default.
Failing to do so will result in a vblank timeout and a stalled display
pipeline.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://lore.kernel.org/r/20211025152903.1088803-11-maxime@cerno.tech
Diffstat (limited to 'drivers/phy/intel/phy-intel-keembay-usb.c')
0 files changed, 0 insertions, 0 deletions