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authorMatteo Croce <mcroce@redhat.com>2019-01-04 22:49:12 +0100
committerLinus Walleij <linus.walleij@linaro.org>2019-01-11 13:25:24 +0100
commit48c67f1fc663d86bbd486a2c664ba130e7c70790 (patch)
tree1bd6445544beda73c51c46a33fc88f519f7aba4e /drivers/pinctrl/pinctrl-amd.c
parent1e11820f72b71d276ae8fdc64fee7cdb49c05bc6 (diff)
pinctrl/amd: fix typo
Fix spelling mistake: "lenght" -> "length" Signed-off-by: Matteo Croce <mcroce@redhat.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-amd.c')
-rw-r--r--drivers/pinctrl/pinctrl-amd.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 2a7d638978d8..6689995fa3aa 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -489,7 +489,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
/*
* If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
* debounce registers of any GPIO will block wake/interrupt status
- * generation for *all* GPIOs for a lenght of time that depends on
+ * generation for *all* GPIOs for a length of time that depends on
* WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the
* INTERRUPT_ENABLE bit will read as 0.
*