diff options
| author | Georgi Djakov <gdjakov@mm-sol.com> | 2014-09-03 19:28:16 +0300 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2014-09-04 18:19:31 +0200 |
| commit | f712c554a7fca8f6308afbce844eacbf5e48787b (patch) | |
| tree | 967825a854c9eba91c242dd920e478dbf03594ff /drivers/pinctrl/qcom/pinctrl-apq8084.c | |
| parent | a9d490c5a8a05b1ff7d2d6fe5bf1053033788e76 (diff) | |
pinctrl: qcom: Make the target processor value configurable
Currently the value used to specify that interrupts from the gpio should
be routed to the application processor is hardcoded for all Qualcomm SoCs.
But the new APQ8084 SoC uses a different value. To resolve this, we make
this value configurable for each SoC. For all existing SoCs we continue
to use the current value, and only for APQ8084 we use the new value.
Suggested-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/qcom/pinctrl-apq8084.c')
| -rw-r--r-- | drivers/pinctrl/qcom/pinctrl-apq8084.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8084.c b/drivers/pinctrl/qcom/pinctrl-apq8084.c index 5362959c448f..138cbf6134a5 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8084.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c @@ -371,6 +371,7 @@ static const unsigned int sdc2_data_pins[] = { 152 }; .intr_status_bit = 0, \ .intr_ack_high = 0, \ .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ .intr_raw_status_bit = 4, \ .intr_polarity_bit = 1, \ .intr_detection_bit = 2, \ @@ -396,6 +397,7 @@ static const unsigned int sdc2_data_pins[] = { 152 }; .intr_enable_bit = -1, \ .intr_status_bit = -1, \ .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ .intr_raw_status_bit = -1, \ .intr_polarity_bit = -1, \ .intr_detection_bit = -1, \ |