diff options
| author | Ulrich Hecht <uli+renesas@fpond.eu> | 2021-01-12 17:59:07 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-01-14 12:06:12 +0100 |
| commit | e127ef2ed0a6099ca6ccc55ff11a812514b6aee6 (patch) | |
| tree | 023829f445a619bebb33775aa540dfde7a73c240 /drivers/pinctrl/renesas/sh_pfc.h | |
| parent | 88a1590b1407207a51788d56746f46cbd6e6ab4e (diff) | |
pinctrl: renesas: Implement unlock register masks
The V3U SoC has several unlock registers, one per register group. They
reside at offset zero in each 0x200 bytes-sized block.
To avoid adding yet another table to the PFC implementation, this
patch adds the option to specify an address mask instead of the fixed
address in sh_pfc_soc_info::unlock_reg.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165912.30876-2-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/pinctrl/renesas/sh_pfc.h')
| -rw-r--r-- | drivers/pinctrl/renesas/sh_pfc.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index dc484c13f59c..1404bd897d25 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -300,7 +300,7 @@ struct sh_pfc_soc_info { const u16 *pinmux_data; unsigned int pinmux_data_size; - u32 unlock_reg; + u32 unlock_reg; /* can be literal address or mask */ }; extern const struct sh_pfc_soc_info emev2_pinmux_info; |