diff options
| author | Tomasz Figa <tomasz.figa@gmail.com> | 2014-10-27 10:21:18 +0900 |
|---|---|---|
| committer | Tomasz Figa <tomasz.figa@gmail.com> | 2014-11-09 22:28:07 +0900 |
| commit | 2891ba2906b6d2fd453042f410a11e6fc3edc37d (patch) | |
| tree | f5c9fd38be386788d355c7ee4af1fcdd7e48bb89 /drivers/pinctrl/samsung/pinctrl-exynos.c | |
| parent | 50cea0cff7131b364c0ff80dedf8e91212b18a26 (diff) | |
pinctrl: exynos: Add support for Exynos4415
The pin controllers of Exynos4415 are similar to Exynos4412, but certain
differences cause the need to create separate driver data for it. This
patch adds pin controller and bank descriptor arrays to the driver to
support the new SoC.
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
[cw00.choi: Rebase it on mainline kernel]
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
[tomasz.figa@gmail.com: Resolved merge with earlier clean-up series.]
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Diffstat (limited to 'drivers/pinctrl/samsung/pinctrl-exynos.c')
| -rw-r--r-- | drivers/pinctrl/samsung/pinctrl-exynos.c | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 5622d8a3e478..d5d4cfc55873 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -918,6 +918,81 @@ const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = { }, }; +/* pin banks of exynos4415 pin-controller 0 */ +static const struct samsung_pin_bank_data exynos4415_pin_banks0[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), + EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), + EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), + EXYNOS_PIN_BANK_EINTG(1, 0x1C0, "gpf2", 0x38), +}; + +/* pin banks of exynos4415 pin-controller 1 */ +static const struct samsung_pin_bank_data exynos4415_pin_banks1[] = { + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08), + EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), + EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), + EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), + EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpl0", 0x18), + EXYNOS_PIN_BANK_EINTN(6, 0x120, "mp00"), + EXYNOS_PIN_BANK_EINTN(4, 0x140, "mp01"), + EXYNOS_PIN_BANK_EINTN(6, 0x160, "mp02"), + EXYNOS_PIN_BANK_EINTN(8, 0x180, "mp03"), + EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "mp04"), + EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "mp05"), + EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "mp06"), + EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), + EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30), + EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos4415 pin-controller 2 */ +static const struct samsung_pin_bank_data exynos4415_pin_banks2[] = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), + EXYNOS_PIN_BANK_EINTN(2, 0x000, "etc1"), +}; + +/* + * Samsung pinctrl driver data for Exynos4415 SoC. Exynos4415 SoC includes + * three gpio/pin-mux/pinconfig controllers. + */ +const struct samsung_pin_ctrl exynos4415_pin_ctrl[] = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos4415_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos4415_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos4415_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos4415_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos4415_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos4415_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, +}; + /* pin banks of exynos5250 pin-controller 0 */ static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = { EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), |