diff options
| author | Abhilash Kesavan <a.kesavan@samsung.com> | 2014-10-09 19:24:29 +0530 |
|---|---|---|
| committer | Tomasz Figa <tomasz.figa@gmail.com> | 2014-11-09 22:26:49 +0900 |
| commit | 0d3d30db93635936652417efd0f4a3e9049d0938 (patch) | |
| tree | 09992cde74688df03c630c7ac0a9b707a48a15b9 /drivers/pinctrl/samsung/pinctrl-samsung.h | |
| parent | 8100cf47698fedbde6dc3fa540b1fefcee69fd40 (diff) | |
pinctrl: exynos: Generalize the eint16_31 demux code
The function exynos_irq_demux_eint16_31 uses pre-defined offsets for external
interrupt pending status and mask registers. So this function is not extensible
for Exynos7 SoC which has these registers at different offsets. Generalize
the exynos_irq_demux_eint16_31 function by using the pending/mask register
offset values from the exynos_irq_chip structure. This is done by adding a
irq_chip field to the samsung_pin_bank struct.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Thomas Abraham <thomas.ab@samsung.com>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Diffstat (limited to 'drivers/pinctrl/samsung/pinctrl-samsung.h')
| -rw-r--r-- | drivers/pinctrl/samsung/pinctrl-samsung.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index ec43b7d49fb9..3076b8b591c7 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -151,6 +151,7 @@ struct samsung_pin_bank_data { * @irq_domain: IRQ domain of the bank. * @gpio_chip: GPIO chip of the bank. * @grange: linux gpio pin range supported by this bank. + * @irq_chip: link to irq chip for external gpio and wakeup interrupts. * @slock: spinlock protecting bank registers * @pm_save: saved register values during suspend */ @@ -171,6 +172,7 @@ struct samsung_pin_bank { struct irq_domain *irq_domain; struct gpio_chip gpio_chip; struct pinctrl_gpio_range grange; + struct exynos_irq_chip *irq_chip; spinlock_t slock; u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/ |